參數(shù)資料
型號(hào)： HD667B66R
廠商： Hitachi,Ltd.
英文描述： 132 x 176-dot Graphics LCD Controller/Driver for 65K Colors
中文描述： 132 × 176點(diǎn)圖形LCD控制器/驅(qū)動(dòng)器的65K色
文件頁數(shù)： 32/97頁
文件大?。?/td> 681K
代理商： HD667B66R
HD66766R Rev. 1.0-1 / September 2002
32
1
st
Screen Driving Position (R14h)
2
nd
Screen Driving Position (R15h)
Figure 17
SS17–0:
Specify the driving start position for the first screen in a line unit. The LCD driving starts from
the 'set value + 1' common driver.
SE17–0:
Specify the driving end position for the first screen in a line unit. The LCD driving is performed
to the 'set value + 1' common driver. For instance, when SS17–10 = “07”H and SE17–10 = “10”H are
set, the LCD driving is performed from COM8 to COM17, and non-selection driving is performed from
COM1 to COM7, COM18 and others. Ensure that SS17–10
≤
SE17–10
≤
“AF”H. For details, see the
Screen-division Driving Function section.
SS27–0:
Specify the driving start position for the second screen in a line unit. The LCD driving starts
from the 'set value + 1' common driver. The second screen is driven when SPT = “1”.
SE27–0:
Specify the driving end position for the second screen in a line unit. The LCD driving is
performed to the 'set value + 1' common driver. For instance, when SPT = “1”, SS27–20 = “20”H, and
SE27–20 = “4F”H are set, the LCD driving is performed from COM33 to COM80. Ensure that SS17–
10
≤
SE17–10
≤
SS27–20
≤
SE27–20
≤
“AF”H. For details, see the Screen-division Driving Function
section.
Horizontal RAM Address Position (R16h)
Vertical RAM Address Position (R17h)
Figure 18 Horizontal/Vertical RAM Address Position Instruction
HSA5-0/HEA5-0:
Specify the horizontal start/end positions of a window for access in memory. Data can
be written to the GRAM from the address specified by HEA7-0 from the address specified by HSA5-0.
Note that an address must be set before RAM is written to. Ensure 00h
≤
HSA7-0
≤
HEA7-0
≤
83h
VSA7-0/VEA7-0:
Specify the vertical start/end positions of a window for access in memory. Data can be
written to the GRAM from the address specified by VEA7-0 from the address specified by VSA7-0. Note
that an address must be set before RAM is written to. Ensure “00”h
≤
VSA7-0
≤
VEA7-0
≤
“AF”h.
W
1
HSA1 HSA0
R/W RS
DB7
DB0
DB6 DB5 DB4 DB3 DB2 DB1
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
HSA2
HSA5 HSA4 HSA3
W
1
VSA1 VSA0
VSA2
VSA6 VSA5 VSA4 VSA3
HEA1 HEA0
HEA2
HEA5 HEA4 HEA3
VSA7
VEA1 VEA0
VEA2
VEA6 VEA5 VEA4 VEA3
VEA7
HSA7 HSA6
HEA7 HEA6
R/W
RS
DB7
DB0
DB6
DB5
DB4 DB3 DB2
DB1
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
W
SS11 SS10
SS12
SS16 SS15 SS14 SS13
SE11 SE10
SE12
SE16 SE15 SE14SE13
SS17
SE17
1
W
1
SS21 SS20
SS22
SS26 SS25 SS24 SS23
SE21SE20
SE22
SE26 SE25 SE24 SE23
SS27
SE27
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