參數(shù)資料
型號(hào)： HD66740WTB0
廠商： Hitachi,Ltd.
英文描述： 112 x 80-dot Graphics LCD Controller/Driver
中文描述： 112 × 80點(diǎn)圖形LCD控制器/驅(qū)動(dòng)器
文件頁數(shù)： 39/95頁
文件大?。?/td> 856K
代理商： HD66740WTB0
HD66740
39
Serial Data Transfer (I2C bus interface)
Setting the IM2=Vcc and IM1=GND level allows I2C bus interface, using the serial data line (SDA) and
serial transfer clock line (SCL). For the I2C bus interface, the IM0/ID pin function uses an ID pin.
The HD66740W is initiated serial data transfer by transferring the first byte when a high SCL level at the
falling edge of the SDA input is sampled; it ends serial data transfer when a high SCL level at the rising
edge of the SDA input is sampled.
Table 16-a illustrates the start byte of I2C bus interface data and Figure 16-a and 16-b show the I2C bus
interface timing sequence.
The HD66740W is selected when the higher 6-bit slave address in the first byte transferred from the
master device match the 6-bits device identification code assigned to the HD66740W. The HD66740W,
when selected, receive the subsequent data string. The lower 1-bit of the device identification code can be
determined by the ID pin; select an appropriate code that is not assigned to any other slave device. The
upper five bits are fixed to 01110. One slave address is assigned to a single HD66740W.
The ninth bit of the first byte is a receive-data acknowledge bit (ACK). When the received slave address
matches the device ID code, HD66740W pulls down the ACK bit to a low level. Therefore, the ACK
output buffer is an open-drain structure, only allowing low-level output. However, the ACK bit is
undermined immediately after power-on; make sure to initialize the LSI using the RESET* input.
After identifying the address in the first byte, the HD66740W receives the subsequent data as an
HD66740W instruction or as RAM data. Having received 8-bit data normally, HD66740W pulls down
the ninth bit (ACK) to a low level. The instruction or RAM data is 8-bits data format.
Two bytes of RAM read data after the start byte are invalid. The HD66740W start to read correct RAM
data from third byte.
Table 16-a Start Byte Format
Transfer Bit
S
1
2
3
4
5
6
7
8
9
Start byte format
Transfer start
Device ID code
RS
R/W
ACK
0
1
1
1
0
ID
Note:
Table 16-b RS and R/W bit function
ID bit is selected by the IM0/ID pin.
RS
R/W
Function
0
0
Writes instruction
0
1
-
1
0
Writes RAM data
1
1
Reads RAM data
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相關(guān)代理商/技術(shù)參數(shù)
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HD66751S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
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