參數(shù)資料
型號(hào): HD66732
廠商: Hitachi,Ltd.
英文描述: Graphics Liquid Crystal Display Controller/Driver Supporting JIS Level-1 and Level-2 Kanji ROM(圖形LCD控制器/驅(qū)動(dòng)器)
中文描述: 圖形液晶顯示控制器/驅(qū)動(dòng)器支持日標(biāo)級(jí)- 1和第2級(jí)漢字光盤(圖形液晶顯示控制器/驅(qū)動(dòng)器)
文件頁(yè)數(shù): 12/133頁(yè)
文件大小: 2608K
代理商: HD66732
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HD66732
12
Pin Functions
Table 2
Pin Functional Description
Signals
Number of
Pins
I/O
Connected to
Functions
IM2, IM1
2
I
V
CC
or GND
Selects the MPU interface mode:
IM2
"GND"
"GND"
"Vcc"
"Vcc"
IM1
"GND"
"Vcc"
"GND"
"Vcc"
MPU interface mode
Clock-synchronized serial interface
68-system parallel bus interface
Setting inhibited
80-system parallel bus interface
IM0/ID
1
I
V
CC
or GND
Inputs the ID of the device ID code for a serial bus
interface. Selects the transfer bus length for a
parallel bus interface.
GND: 8-bit bus, Vcc: 4-bit bus
Selects the HD66732:
Low: HD66732 is selected and can be accessed
High: HD66732 is not selected and cannot be
accessed
Must be fixed at GND level when not in use.
Selects the register for a parallel bus interface.
Low: Instruction
High: RAM access
Selects the key scan interrupt method in the standby
period for a serial interface. Monitors a total of eight
keys connected to KST0 at the GND level and
monitors all keys at the Vcc level to generate an
interrupt. Must be fixed at the GND or Vcc level.
Inputs the serial transfer clock for a serial interface.
Fetches data at the rising edge of a clock.
For a 68-system parallel bus interface, serves as an
enable signal to activate data read/write operation.
For an 80-system parallel bus interface, serves as a
write strobe signal and writes data at the low level.
Serves as the bidirectional serial transfer data for a
serial interface. Sends/Receives data.
For a 68-system parallel bus interface, serves as a
signal to select data read/write operation.
For an 80-system parallel bus interface, serves as a
write strobe signal and reads data at the low level.
Generates the key scan interrupt signal.
Generates strobe signals for latching scanned data
from the key matrix at specific time intervals.
Available for a serial interface only.
Samples key state from key matrix synchronously
with strobe signals for a serial interface.
Serves as a bidirectional data bus for a parallel bus
interface.
For a 4-bit bus, data transfer uses KIN7/DB7-
KIN4/DB4; leave KIN3/DB3-KIN0/DB0 disconnected.
CS*
1
I
MPU
RS
1
I
MPU
E/WR*/SCL 1
I
MPU
RW/RD*/
SDA
1
I or
I/O
MPU
IRQ*
KST0–
KST3
1
4
O
O
MPU
Key matrix
DB0/KIN0–
DB7/KIN7
8
I or
I/O
Key matrix or
MPU
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