參數(shù)資料
型號(hào): HD66710A00TF
廠商: Hitachi,Ltd.
英文描述: (Dot Matrix Liquid Crystal Display Controller/Driver)
中文描述: (點(diǎn)陣式液晶顯示控制器/驅(qū)動(dòng)器)
文件頁(yè)數(shù): 36/73頁(yè)
文件大?。?/td> 507K
代理商: HD66710A00TF
HD66710
326
N:
When bit NW in the extended function set is 0, a 1- or a 2-line display is set. When N is 0, 1-line
display is selected; when N is 1, 2-line display is selected. When NW is 1, a 4-line display is set. At this
time, N is “Don’t care”.
RE:
When the RE bit is 1, bit BE and LP in the extended function set registe, the SEGRAM address set
register, and the extended function set register can be accessed. When bit RE is 0, the registers described
above cannot be accessed, and the data in these registers is held.
To maintain compatibility with the HD44780, the RE bit should be fixed to 0.
Clear display, return home and cursor or display shift instruction a reset the RE bit to 0.
BE:
When the RE bit is 1, this bit can be rewritten. When this bit is 1, the user font in CGRAM and the
segment in SEGRAM can be blinked according to the upper two bits of CGRAM and SEGRAM.
LP:
When the RE bit is 1, this bit can be rewritten. When LP is set to 1 and the EXT pin is low (without
an extended driver), the HD66710 operates in low power mode. In 1-line display mode, the HD66710
operates on a 4-division clock, and in a 2-line or a 4-line display mode, the HD66710 operates on a 2-
division clock. According to these operations, instruction execution takes four times or twice as long.
Notice that in a low power mode, display shift cannot be performed.
Note:
Perform the DL, N, NW, FW functions at the head of the program before executing any
instructions (except for the read busy flag and address instruction). From this point, if bit N, NW,
or FW is changed after other instructions are executed, RAM contents may be lost.
After changing the N or NW or LP bit, please issue the return home or clear display instruction
cancel to shift display.
Set CGRAM Address
A CGRAM address can be set while the RE bit is cleared to 0. Set CGRAM address sets the CGRAM
address binary AAAAAA into the address counter.
Data is then written to or read from the MPU for CGRAM.
Table 9
Display Line Set
N
NW
No. of
Display
Lines
Character
Font
5
×
8 dots
5
×
8 dots
5
×
8 dots
Duty
Factor
Maximum Number of Characters/1
Line with Extended Drivers
0
0
1
1/17
50 characters
1
0
2
1/33
30 characters
*
Note:
1
4
1/33
20 characters
*
Indicates don’t care.
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參數(shù)描述
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