
Table 20-10
Timing Conditions of On-Chip
Supporting Modules
– Preliminary for S-Mask Versions–
Condition A (R-mask):
V
CC
= 5.0 V ±10%, = 0.5 to 10 MHz, V
SS
= 0 V,
T
a
= –20 to +75C(Regular Specifications),
T
a
= –40 to +85C (Wide-Range Specifications)
V
CC
= 5.0 V ±10%, = 2.0 to 16 MHz, V
SS
= 0 V,
T
a
= –20 to +75C (Regular Specifications),
T
a
= –40 to +85C (Wide-Range Specifications)
V
CC
= 3.0 to 5.5 V, = 2.0 to 10 MHz, V
SS
= 0 V,
T
a
= –20 to +75C (Regular Specifications)
Condition B (5-V S-mask):
Condition C (3-V S-mask):
Condition D (2.7-V S-mask): V
CC
= 2.7 to 5.5 V, = 2.0 to 8 MHz, V
SS
= 0 V,
T
a
= –20 to +75C (Regular Specifications)
Condition A
Condition D
8 MHz
Min
–
Condition C
10 MHz
Min
–
Condition B
16 MHz
Min
–
6 MHz
Item
FRT
Symbol
Min
t
FTOD
Max
100
Max
100
Max
100
Max
100
Unit
ns
Timer output
delay time
Timer input
setup time
Timer clock
input setup time
Timer clock
pulse width
Timer output
delay time
Timer clock
input setup time
Timer clock
pulse width
Timer reset
input setup time
Timer output
delay time
–
See figure
20-14
t
FTIS
50
–
50
–
50
–
50
–
ns
t
FTCS
50
–
50
–
50
–
50
–
ns
See figure
20-15
t
FTCWL
,
t
FTCWH
t
TMOD
1.5
–
1.5
–
1.5
–
1.5
–
tcyc
TMR
–
100
–
100
–
100
–
100
ns
See figure
20-16
See figure
20-17
t
TMCS
50
–
50
–
50
–
50
–
ns
t
TMCWL
, 1.5
t
TMCWH
t
TMRS
–
1.5
–
1.5
–
1.5
–
tcyc
50
–
50
–
50
–
50
–
ns
See figure
20-18
See figure
20-19
PWM
t
PWOD
–
100
–
100
–
100
–
100
ns
Test
Conditions
346