
69
Bits 4 to 0:
IRQ
4
to IRQ
0
interrupt request flags (IRRI4 to IRRI0)
Bit n
IRRIn
Description
0
Clearing conditions:
When IRRIn = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When pin
IRQn
is designated for interrupt input and the designated
signal edge is input
(n = 4 to 0)
Note:
IRQ
is an internal signal that performs interfacing to the FLEX
decoder incorporated in
the chip.
5. Interrupt request register 2 (IRR2)
Bit
Initial value
Read/Write
7
IRRDT
0
R/(W)
*
6
IRRAD
0
R/(W)
*
5
—
0
R/W
4
IRRTG
0
R/(W)
*
3
IRRTFH
0
R/(W)
*
0
IRREC
0
R/(W)
*
2
IRRTFL
0
R/(W)
*
1
IRRTC
0
R/(W)
*
Note:
*
Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FC, or Timer C interrupt is requested. The
flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear
each flag.
Bit 7:
Direct transfer interrupt request flag (IRRDT)
Bit 7
IRRDT
Description
0
Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
(initial value)
1
Setting conditions:
When a direct transfer is made by executing a SLEEP instruction
while DTON = 1 in SYSCR2