
5
1.2
Block Diagram
Figure 1.1 shows a block diagram of the H8/3437 Series.
PB
0
/XDB
0
PB
1
/XDB
1
PB
2
/XDB
2
PB
3
/XDB
3
PB
4
/XDB
4
PB
5
/XDB
5
PB
6
/XDB
6
PB
7
/XDB
7
P9
0
/
ADTRG
/
ECS
2
/
IRQ
2
P9
1
/
IRQ
1
/
EIOW
P9
2
/
IRQ
0
P9
3
/
RD
P9
4
/
WR
P9
5
/
AS
P9
6
/
P9
7
/
WAIT
/SDA
P3
0
/D
0
/HDB
0
P3
1
/D
1
/HDB
1
P3
2
/D
2
/HDB
2
P3
3
/D
3
/HDB
3
P3
4
/D
4
/HDB
4
P3
5
/D
5
/HDB
5
P3
6
/D
6
/HDB
6
P3
7
/D
7
/HDB
7
P8
0
/HA
0
P8
1
/GA
20
P8
2
/
1
P8
3
/IOR
P8
4
/TxD
1
/
IRQ
3
/
IOW
P8
5
/RxD
1
/
IRQ
4
/
CS
2
P8
6
/SCK
1
/
IRQ
5
/SCL
PA
0
/
KEYIN
8
PA
1
/
KEYIN
9
PA
2
/
KEYIN
10
PA
3
/
KEYIN
11
PA
4
/
KEYIN
12
PA
5
/
KEYIN
13
PA
6
/
KEYIN
14
PA
7
/
KEYIN
15
P1
0
/A
0
P1
1
/A
1
P1
2
/A
2
P1
3
/A
3
P1
4
/A
4
P1
5
/A
5
P1
6
/A
6
P1
7
/A
7
P2
0
/A
8
P2
1
/A
9
P2
2
/A
10
P2
3
/A
11
P2
4
/A
12
P2
5
/A
13
P2
6
/A
14
P2
7
/A
15
KEYIN
0
/P6
0
/FTCI
KEYIN
1
/P6
1
/FTOA
KEYIN
2
/P6
2
/FTIA
KEYIN
3
/P6
3
/FTIB
KEYIN
4
/P6
4
/FTIC
KEYIN
/P6
5
/FTID
KEYIN
/P6
6
/FTOB/
IRQ
6
KEYIN
7
/P6
7
/
IRQ
7
P
0
/
0
P
1
/
0
P
2
/
0
H
1
/
3
/
1
H
1
/
4
/
1
H
1
/
5
/
1
P
6
/
0
P
7
/
1
P
7
/
7
/
1
P
6
/
6
/
0
P
5
/
5
P
4
/
4
P
3
/
3
P
2
/
2
P
1
/
1
P
0
/
0
P
0
/
0
P
1
/
0
P
2
/
0
A
r
A
C
A
S
R
R
S
N
M
0
M
1
V
C
B
V
C
V
C
V
S
V
S
V
S
V
S
X
E
P
P
P
P
Data bus (low)
RAM
H8/3437: 2 kbytes
H8/3436: 2 kbytes
H8/3434: 1 kbyte
10-bit
A/D converter
(8 channels)
8-bit
D/A converter
(2 channels)
16-bit
free-running
timer
8-bit timer
(2 channels)
PWM timer
(2 channels)
C
g
H8/3437
60 kbytes
2 kbytes
H8/3436
48 kbytes
2 kbytes
H8/3434
32 kbytes
1 kbyte
Memory Sizes
ROM
RAM
ROM
(flash memory,
PROM, or
mask ROM)
H8/3437: 60 kbytes
H8/3436: 48 kbytes
H8/3434: 32 kbytes
Watchdog
timer
Host
interface
Serial
communication
interface (2 channels)
I
2
C bus interface
(1 channel) [option]
Port 4
Port 7
Port 5
P
P
P
P
CPU
H8/300
D
A
Figure 1.1 Block Diagram