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參數(shù)資料
| 型號(hào)： | HD49323AF |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | CDS/AGC & 10-bit A/D Converter |
| 中文描述： | 的CDS /自動(dòng)增益控制 |
| 文件頁數(shù)： | 13/27頁 |
| 文件大?。?/td> | 104K |
| 代理商： | HD49323AF |
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HD49323AF-01
13
Table 5
Each Timing Specifications
No.
Timing
Symbol
Min
Typ
Max
Unit
Note
(1)
Black level signal read-in time
t
CDS1
t
CDS2
t
CDS3
t
CDS4
t
CDS5
t
CDS6-1
t
CDS6-2
t
CDS7, 8
0
5
10
ns
1
(2)
SPBLK “Lo” period
11
1/4f
ADCLK
5
Typ
×
1.2
ns
2
(3)
Signal level read-in time
0
10
ns
1
(4)
SPSIG “Lo” period
11
1/4f
ADCLK
1/2f
ADCLK
—
Typ
×
1.2
Typ
×
1.15
ns
2
(5)
SPBLK rise to SPSIG rise
20
ns
2
(6)-1
ADCLK rise to SPBLK rise
25
—
ns
2
(6)-2
SPSIG rise to ADCLK rise
0
ns
2
(7), (8)
Note:
ADCLK t
WH
Min / t
WL
Min
1. Negative when data before the rising edge of SPBLK/SPSIG is sampled, and positive when data
after the rising edge is sampled.
2. The polarity of SPBLK and SPSIG is for a low setting of the serial data SP INV bit.
22
ns
SPBLK
SPSIG
+
1.4V
Detailed Timing Specifications for Digital Output Enable Control
Detailed timing specifications in the case of digital output enable control are shown in figure 5. When the
OE
pin is high, output disable mode is entered and output goes to the high-Z state.
Digital output
(D0 to D9)
OE
t
LZ
t
ZL
t
HZ
t
ZH
1.4V
×
DV
DD
3.0V
DV
DD
/2
DV
DD
/2
DV
DD
2k
10pF
DV
DD
DV
SS
DV
SS
V
OL
t
, t
measurement load
t
, t
measurement load
V
OH
DV
SS
10pF
2k
DV
SS
Figure 5 Detailed Timing Specifications for Digital Output Enable Control
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| HD49323AF-01 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:CDS/AGC & 10-bit A/D Converter |
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