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參數(shù)資料
| 型號(hào)： | HD49319F |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | CMOS 9-Bit A/D Converter(CMOS 9位A/D轉(zhuǎn)換器) |
| 中文描述： | 的CMOS 9位A / D轉(zhuǎn)換器的CMOS（9位的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 70K |
| 代理商： | HD49319F |
HD49319F
6
Electrical Characteristics
(Unless otherwise specified, V
DD
= 5.0 V, DV
DD2
= 3.3 V,
V
RT
= 3.0 V, V
RB
= 0.0 V, Ta = 25
°
C, and the internal op-amp is unused.) (cont)
Item
Symbol
Min
Typ
Max
Units
Measurement Conditions Note
Digital input current
I
IH
I
IL
I
IL(
RST
)
I
OP
f
CLK(max)
–50
—
50
μ
A
μ
A
μ
A
μ
A
V
IH
= V
DD
V
IL
= 0 V
V
IL
= 0 V
VRTin = 3 V
–50
—
50
–200
—
50
Op-amp input current
–50
—
50
Maximum conversion
speed
15
—
—
MHz
1
Minimum conversion
speed
f
CLK(min)
—
—
0.5
MHz
Minimum clock pulse
t
WH(min)
t
WL(min)
t
WH(max)
t
WL(max)
—
—
30
ns
width
—
—
30
ns
Maximum clock pulse
1
—
—
μ
s
μ
s
width
1
—
—
Digital output delay time t
PD
Digital output hold time
—
—
38
ns
Load capacitance = 10 pF
t
HOLD
t
AP
8
—
—
ns
Analog signal read-in
time
–5
6
10
ns
Integration linearity
I
NL
DNL
—
2
5.5
LSBpp f
CLK
= 15 MHz
LSB
Differentiation linearity
–0.7
—
+0.7
Reset pulse width
T
RH
T
RL
3
×
1/f
CLK
—
3
×
1/f
CLK
—
—
—
Notes: *1. I
DD1
is Quiescent current of V
DD
.
*2. I
DD2
is Quiescent current of DV
DD2
.
*3. I
IN
is not transition current, but static current.
*4. In case of
V
DD
– 1V > DV
DD2
→
V
X
= DV
DD2
V
DD
– 1V < DV
DD2
→
V
X
= V
DD
1. With the change in input voltage between conversions on each clock 2.2 V or less.
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