參數(shù)資料
型號(hào): HD49235
廠商: Hitachi,Ltd.
英文描述: 16 AMP SPDT MINIATURE POWER RELAY
中文描述: 數(shù)字信號(hào)處理器的CD
文件頁(yè)數(shù): 8/41頁(yè)
文件大小: 192K
代理商: HD49235
HD49235FS
Rev.2, Aug. 1995, page 8 of 41
Microprocessor Commands
Data
Register
(Address) Command
D7
D6
D5
D4
D3
D2
D1
D0
SENS
Pin
Output
8 (1000)
Mode
selections
ROM
ROMEF
DOOFF
SUBCO
SLTSW
0
DCOND
DWIDTH
Z
9 (1001)
Function
selections
1
BI1
BI0
WG10TL SYLCK1
SYLCK0 CRCQ
*
Z
A (1010)
Audio
control
MUTEL
MUTER
MONO
ATT
BLGMAIN BLGSUB SOFTMT SWLR
Z
B (1011)
Track
counter
setting
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
Complete
C (1100)
CLV control AINTV
ATH
GAIN1
GAIN0
SGAIN1
SGAIN0
PDGAIN1 PDGAIN0 Count
D (1101)
CLV kick
control
KICK7
KICK6
KICK5
KICK4
KICK3
KICK2
KICK1
*
Z
E (1110)
CLV mode
ED3
ED2
ED1
ED0
0
*
*
*
BRAKE
F (1111)
ECU mode
0
0
AS0
*
*
*
*
*
Z
Asterisks indicate don’t-care bits
Register 8
0
1
ROM
D7
Audio (with interpolation)
CD-ROM (no interpolation)
ROMEF
D6
C2 flag output order: lower first
C2 flag output order: upper first
DOOFF
D5
Digital output on
Digital output off
SUBCO
D4
Subcode data not inserted in DAS signal
Subcode data inserted in DAS signal
SLTSW
D3
48-fs clock
64-fs clock
D2
Normal operation
Illegal setting
DCOND
D1
Condition for switching between digital and
analog PLLs: digital PLL when defect
detection signal width is 4 frames or more
Condition for switching between digital and
analog PLLs: digital PLL when defect
detection signal width is 8 frames or more
DWIDTH
D0
Digital PLL termination timing:
8 frames after fall of defect detection
signal if width of defect detection signal
width is less than 12 frames
16 frames after fall of defect detection
signal if width of defect detection signal
width is 12 frames or more
4 frames after fall of defect detection
signal if width of defect detection signal
width is less than 12 frames
8 frames after fall of defect detection
signal if width of defect detection signal
width is 12 frames or more
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