參數(shù)資料
型號: HD40A4638R
廠商: Hitachi,Ltd.
英文描述: 4-Bit Single-Chip Microcomputer(4位單片微計算機(jī))
中文描述: 4位單片機(jī)(4位單片微計算機(jī))
文件頁數(shù): 24/133頁
文件大小: 803K
代理商: HD40A4638R
HD404639R Series
24
Timer D Interrupt Request Flag (IFTD: $003, Bit 0):
Set by overflow output from timer D, or by the
rising or falling edge of signals input to EVND when the input capture function is used, as listed in table
13.
Table 13 Timer D Interrupt Request Flag (IFTD: $003, Bit 0)
IFTD
Interrupt Request
0
No
1
Yes
Timer D Interrupt Mask (IMTD: $003, Bit 1):
Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 14.
Table 14 Timer D Interrupt Mask (IMTD: $003, Bit 1)
IMTD
Interrupt Request
0
Enabled
1
Disabled (masked)
Serial Interrupt Request Flags (IFS1: $003, Bit 2; IFS2: $023, Bit 2):
Set when data transfer is
completed or when data transfer is suspended, as listed in table 15.
Table 15 Serial Interrupt Request Flag (IFS1: $003, Bit 2; IFS2: $023, Bit 2)
IFS1, IFS2
Interrupt Request
0
No
1
Yes
Serial Interrupt Masks (IMS1: $003, Bit 3; IMS2: $023, Bit 3):
Prevents (masks) an interrupt request
caused by the serial interrupt request flag, as listed in table 16.
Table 16 Serial Interrupt Mask (IMS1: $003, Bit 3; IMS2: $023, Bit 3)
IMS1, IMS2
Interrupt Request
0
Enabled
1
Disabled (masked)
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