參數(shù)資料
型號： HD404849FS
廠商： Hitachi,Ltd.
元件分類： 其它接口
英文描述： TERMINAL
中文描述： IGBT模塊
文件頁數(shù)： 47/125頁
文件大?。?/td> 471K
代理商： HD404849FS
HD404849 Series
47
I/O Pin Type
Circuit
Pins
INT
0
,
STOPC
Peripheral
function pins
Input
pins
Input data
INT
0
,
STOPC
HLT
MIS3
PDR
SI, etc.
V
CC
SI,
INT
, INT
2
,
INT
,
EVNB
,
EVND
A/D input
Input control
AN
0
–AN
3
HLT
MIS3
PDR
A/D input
Input control
V
CC
AN
4
–AN
7
Note: The MCU is reset in stop mode, and an peripheral function selections are cancelled. The I/O control
register is reset, so the input/output pins enter high-impedance state.
D Port:
Consist of nine input/output pins and two input pins addressed by one bit. D
0
–D
8
are high-current
I/O pins, and D
10
and D
11
are input-only pins.
Pins D
0
–D
8
are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. All pins of the D port are tested by the TD
and TDD instructions.
The on/off statuses of the output buffers are controlled by D port data control registers (DCD0–DCD2:
$02C–$02E) that are mapped to memory addresses (figure 29).
Pins D
10
and D
11
are multiplexed with peripheral function pins
STOPC
and
I NT
0
, respectively. The
peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 34).
R Ports:
24 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR
instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data
register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R
port data control registers (DCR0–DCR3, DCR6, DCR7: $030–$033, $036, $037) that are mapped to
memory addresses (figure 29).
相關(guān)PDF資料
PDF描述
HD404849H SPLICE
HD404849TF TERMINAL
HD4074849 TERMINAL
HD4074849FS CONTACT
HD4074849H CONTACT
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