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參數(shù)資料
| 型號(hào)： | HD404849 |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | 其它接口 |
| 英文描述： | TERMINAL |
| 中文描述： | IGBT模塊 |
| 文件頁(yè)數(shù)： | 19/125頁(yè) |
| 文件大?。?/td> | 471K |
| 代理商： | HD404849 |
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HD404849 Series
19
Interrupts
The MCU has ten interrupt sources: four external signals (
INT
0
,
INT
1
,
INT
2
, INT
3
), four timer/counters
(timers A, B, C, and D), serial interface, and A/D converter.
An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.
Some vector addresses are shared by two different interrupts. They are timer B and INT
2
, timer C and
INT
3
, and A/D converter and serial interface interrupts. So the type of request that has occurred must be
checked at the beginning of interrupt processing.
Interrupt Control Bits and Interrupt Processing:
Locations $000 to $003 and $022 to $023 in RAM are
reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.
The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.
A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the ten interrupt sources are listed in
table 3.
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.
The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in
figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.
Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
Table 2 Vector Addresses and Interrupt Priorities
Reset/Interrupt
RESET
,
STOPC
*
INT
0
INT
1
Timer A
Timer B, INT
2
Timer C, INT
3
Timer D
A/D, Serial
Note:
*
The
STOPC
interrupt request is valid only in stop mode.
Priority
—
1
2
3
4
5
6
7
Vector Address
$0000
$0002
$0004
$0006
$0008
$000A
$000C
$000E
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD404849FS | TERMINAL |
| HD404849H | SPLICE |
| HD404849TF | TERMINAL |
| HD4074849 | TERMINAL |
| HD4074849FS | CONTACT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD404849FS | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4-Bit Single-Chip Microcomputer |
| HD404849H | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4-Bit Single-Chip Microcomputer |
| HD404849SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| HD404849TF | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-Bit Single-Chip Microcomputer |
| HD404868 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Low-Voltage AS Microcomputers with On-Chip LCD Circuit |
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