參數(shù)資料
型號: HD404829R
廠商: Hitachi,Ltd.
英文描述: AS Microcomputer Incorporating a LCD controller/Driver Circuit(帶LCD控制/驅(qū)動電路的微計算機)
中文描述: 由于微機安裝有LCD控制器/驅(qū)動電路(帶液晶控制/驅(qū)動電路的微計算機)
文件頁數(shù): 84/147頁
文件大小: 519K
代理商: HD404829R
HD404829R Series
84
Table 22 Serial Interface Operating Modes
SMRA
PMRA
Bit 3
Bit 1
Bit 0
Operating Mode
1
0
0
Continuous clock output mode
1
Transmit mode
1
0
Receive mode
1
Transmit/receive mode
Transfer Control:
The serial interface is activated by the STS instruction. The octal counter is reset to
000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit
clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,
the serial interrupt request flag (IFS: $023, bit 2) is set, and the transfer stops.
When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t
cyc
to 8192t
cyc
by setting bits 2 to 0 (SMRA2– SMRA0) of serial mode register A (SMRA: $005) and bit 0
(SMRB0) of serial mode register B (SMRB: $028) as listed in table 23.
Table 23 Serial Transmit Clock (Prescaler Output)
SMRB
SMRA
Bit 0
Bit 2
Bit 1
Bit 0
Prescaler Division Ratio
Transmit Clock Frequency
0
0
0
0
÷
2048
÷
512
÷
128
÷
32
÷
8
÷
2
÷
4096
÷
1024
÷
256
÷
64
÷
16
÷
4
4096t
cyc
1024t
cyc
256t
cyc
64t
cyc
16t
cyc
4t
cyc
8192t
cyc
2048t
cyc
512t
cyc
128t
cyc
32t
cyc
8t
cyc
1
1
0
1
1
0
0
1
1
0
0
0
1
1
0
1
1
0
0
1
Operating States:
The serial interface has the following operating states; transitions between them are
shown in figure 71.
STS wait state
Transmit clock wait state
Transfer state
Continuous clock output state (only in internal clock mode)
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