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參數(shù)資料
| 型號(hào)： | HD404368 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4-bit HMCS400-Series microcomputer(4位單片微計(jì)算機(jī)) |
| 中文描述： | 4位HMCS400系列微機(jī)（4位單片微計(jì)算機(jī)） |
| 文件頁(yè)數(shù)： | 57/115頁(yè) |
| 文件大?。?/td> | 710K |
| 代理商： | HD404368 |
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HD404369 Series
57
Timer B
Timer B Functions:
Timer B has the following functions.
Free-running/reload timer
External event counter
Input capture timer
The block diagram for each operation mode of timer B is shown in figures 38 and 39.
Timer B Operations:
Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register B1 (TMB1: $009).
Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by
software and incremented by one at each clock input. If an input clock is applied to timer B after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is
initialized to its initial value set in timer write register B; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
External event counter operation: Timer B is used as an external event counter by selecting the external
event input as an input clock source. In this case, pin D
2
/EVNB must be set to EVNB by port mode
register B (PMRB: $024).
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by timer mode register 2 (TMB2: $026). When both rising and falling
edges detection is selected, the time between the falling edge and rising edge of input signals must be
2t
cyc
or longer.
Timer B is incremented by one at each detection edge selected by timer mode register 2 (TMB2: $026).
The other operation is basically the same as the free-running/reload timer operation.
Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVNB.
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by timer mode register 2 (TMB2: $026).
When a trigger edge is input to EVNB, the count of timer B is written to timer read register B (TRBL:
$00A, TRBU: $00B), and the timer B interrupt request flag (IFTB: $002, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer B is reset to $00, and then incremented again. While ICSF
is set, if a trigger input edge is applied to timer B, or if timer B generates an overflow, the input capture
error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0.
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| HD40A4368 | 4-bit HMCS400-Series microcomputer(4位單片微計(jì)算機(jī)) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD404368F | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4-bit HMCS400-Series microcomputer |
| HD404368H | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:microcomputer has an A/D converter |
| HD404368S | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4-bit HMCS400-Series microcomputer |
| HD404369 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:microcomputer has an A/D converter |
| HD404369F | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4-bit HMCS400-Series microcomputer |
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