![](http://datasheet.mmic.net.cn/280000/HD40A4052_datasheet_16064714/HD40A4052_66.png)
HD404054 Series/HD404094 Series
66
Table 26
Serial Transmit Clock (prescaler output)
SM1B
SM1A
Bit 0
Bit 2
Bit 1
Bit 0
Prescaler Division Ratio
Tranamit Clock Frequency
0
0
0
0
÷
2048
÷
512
÷
128
÷
32
÷
8
÷
2
÷
4096
÷
1024
÷
256
÷
64
÷
16
÷
4
4096t
cyc
1024t
cyc
256t
cyc
64t
cyc
16t
cyc
4t
cyc
8192t
cyc
2048t
cyc
512t
cyc
128t
cyc
32t
cyc
8t
cyc
1
1
0
1
1
0
0
1
1
0
0
0
1
1
0
1
1
0
0
1
Operating States:
Serial interface 1 has the following operating states; transitions between them are
shown in figure 50.
STS wait state
Transmit clock wait state
Transfer state
Continuous transmit clock output state (only in internal clock mode)
STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 50). In STS
wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then
executed (01, 11), serial interface 1 enters transmit clock wait state.
Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge
of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments
the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the serial interface
in transfer state. However, note that if continuous clock output mode is selected in internal clock mode,
the serial interface does not enter transfer state but enters continuous clock output state (17).
The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04,
14) in transmit clock wait state.
Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the
eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the
octal counter to 000, and the serial interface enters another state. When the STS instruction is executed
(05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is
entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.