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參數(shù)資料
| 型號(hào)： | HD151011 |
| 廠商： | Hitachi,Ltd. |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Dual BCD Programmable Counter with Synchronous Preset Enable(帶同步使能預(yù)置的可編程雙BCD計(jì)數(shù)器) |
| 中文描述： | 雙BCD碼可編程計(jì)數(shù)器的同步預(yù)置啟用（帶同步使能預(yù)置的可編程雙BCD碼計(jì)數(shù)器） |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 75K |
| 代理商： | HD151011 |
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HD151011
2
Function Table
Control Inputs
CLR
PR
SPE
C/
T
Mode
Operation Description
H
H
H
X
Generally count
Down count at the rise edge of clock (CLK),
Down count at the fall edge of clock (
CLK
)
X
X
L
X
Synchronous preset
Jn data is preset at the rise of clock (CLK),
the fall of clock (
CLK
)
Clock inputs (CLK,
CLK
) is CMOS level
Clock inputs (CLK,
CLK
) is TTL level
—
—
—
H
—
—
—
—
L
—
L
H
—
—
Initialize of Q output
Initialize of Q = "L"
H
H: High level
L: Low level
Z: Immaterial
—: Irrespective of condition
1. Synchronous preset (
SPE
) input can set max 99 down counts.
2. When the count value is 0, the next clock pulse presets the data to invert the output.
3. CLR and PR inputs initialize output state.
4. Clock inputs (CLK,
CLK
) is selectable CMOS level (V
CC
= 2.0 to 6.0 V) and TTL level (V
CC
= 4.5 to 5.5V)
(Jn, C/
T
, PR, CLR and
SPE
inputs are CMOS level)
Note:
Don't set data exceeding 99 to Jn. (J0: LSB, J7: MSB)
L
—
—
Initialize of Q output
Initialize of Q = "H"
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HD151011FPEL | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Dual BCD Programmable Counter with Synchronous Preset Enable |
| HD151011TELL | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Dual BCD Programmable Counter with Synchronous Preset Enable |
| HD151011TELL-E | 制造商:Renesas Electronics Corporation 功能描述:Counter Single 1-Bit Sync Decade Down 20-Pin TSSOP T/R |
| HD151012 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:8-bit Binary Programmable Counter with Synchronous Preset Enable |
| HD151012TELL | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:8-bit Binary Programmable Counter with Synchronous Preset Enable |
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