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參數(shù)資料
| 型號(hào)： | HCTS02HMSR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Radiation Hardened Quad 2-Input NOR Gate |
| 中文描述： | HCT SERIES, QUAD 2-INPUT NOR GATE, UUC14 |
| 封裝： | DIE-14 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 75K |
| 代理商： | HCTS02HMSR |
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
HCTS02MS
Radiation Hardened
Quad 2-Input NOR Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
Functional Diagram
TRUTH TABLE
INPUTS
OUTPUTS
An
Bn
Yn
L
L
H
L
H
L
H
L
L
H
H
L
NOTE: L = Logic Level Low, H = Logic level High
Y1
A1
B1
Y2
A2
B2
GND
VCC
Y4
B4
A4
Y3
B3
A3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
Y1
A1
B1
Y2
A2
B2
GND
VCC
Y4
B4
A4
Y3
B3
A3
(2, 5, 8, 11)
An
(3, 6, 9, 12)
Bn
Yn
(1, 4, 10, 13)
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD(Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day
(Typ)
Dose Rate Survivability: >1 x 10
12
Rads (Si)/s
Dose Rate Upset >10
10
RAD(Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCTS02MS is a Radiation Hardened Quad 2-Input
NOR Gate. A low on both inputs forces the output to a High state.
The HCTS02MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS02MS is supplied in a 14 lead Ceramic Flatpack Pack-
age (K suffix) or a 14 lead SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
SCREENING
LEVEL
PACKAGE
HCTS02DMSR
-55
o
C to +125
o
C
Intersil Class
S Equivalent
14 Lead SBDIP
HCTS02KMSR
-55
o
C to +125
o
C
Intersil Class
S Equivalent
14 Lead Ceramic
Flatpack
HCTS02D/
Sample
+25
o
C
Sample
14 Lead SBDIP
HCTS02K/
Sample
+25
o
C
Sample
14 Lead Ceramic
Flatpack
HCTS02HMSR
+25
o
C
Die
Die
August 1995
D
Spec Number
518841
File Number
2137.2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCTS10D | Dual Positive-Edge-Triggered D-Type- Flip-Flops With Clear And Preset 14-CDIP -55 to 125 |
| HCTS10DMSR | Radiation Hardened Triple 3-Input NAND Gate |
| HCTS10HMSR | Radiation Hardened Triple 3-Input NAND Gate |
| HCTS10K | Radiation Hardened Triple 3-Input NAND Gate |
| HCTS10KMSR | Radiation Hardened Triple 3-Input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCTS02K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input NOR Gate |
| HCTS02KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input NOR Gate |
| HCTS02MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad 2-Input NOR Gate |
| HCTS04D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Hex Inverter |
| HCTS04DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Hex Inverter |
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