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參數(shù)資料
| 型號(hào)： | HCT4511 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | BCD to 7-segment latch/decoder/driver |
| 中文描述： | BCD碼至7段鎖存器/解碼器/驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 80K |
| 代理商： | HCT4511 |
December 1990
2
Philips Semiconductors
Product specification
BCD to 7-segment latch/decoder/driver
74HC/HCT4511
FEATURES
Latch storage of BCD inputs
Blanking input
Lamp test input
Driving common cathode LED displays
Guaranteed 10 mA drive capability per output
Output capability: non-standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4511 are high-speed Si-gate CMOS
devices and are pin compatible with “4511” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4511 are BCD to 7-segment
latch/decoder/drivers with four address inputs (D
1
to D
4
),
an active LOW latch enable input (LE), an active LOW
ripple blanking input (BI), an active LOW lamp test input
(LT), and seven active HIGH segment outputs (Q
a
to Q
g
).
When LE is LOW, the state of the segment outputs (Q
a
to
Q
g
) is determined by the data on D
1
to D
4
.
When LE goes HIGH, the last data present on D
1
to D
4
are
stored in the latches and the segment outputs remain
stable.
When LT is LOW, all the segment outputs are HIGH
independent of all other input conditions. With LT HIGH, a
LOW on BI forces all segment outputs LOW. The inputs LT
and BI do not affect the latch circuit.
APPLICATIONS
Driving LED displays
Driving incandescent displays
Driving fluorescent displays
Driving LCD displays
Driving gas discharge displays
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
D
n
to Q
n
LE to Q
n
BI to Q
n
LT to Q
n
input capacitance
power dissipation capacitance per latch
C
L
= 15 pF; V
CC
= 5 V
24
23
19
12
3.5
64
24
24
20
13
3.5
64
ns
ns
ns
ns
pF
pF
C
I
C
PD
notes 1 and 2
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