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參數(shù)資料
| 型號： | HCT4016 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quad bilateral switches |
| 中文描述： | 四雙邊開關(guān) |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 109K |
| 代理商： | HCT4016 |
December 1990
2
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4016
FEATURES
Low “ON” resistance:
160
(typ.) at V
CC
= 4.5 V
120
(typ.) at V
CC
= 6.0 V
80
(typ.) at V
CC
= 9.0 V
Individual switch controls
Typical “break before make” built in
Output capability: non-standard
I
CC
category: SSI
GENERAL DESCRIPTION
The 74HC/HCT4016 are high-speed Si-gate CMOS
devices and are pin compatible with the “4016” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4016 have four independent analog
switches (transmission gates).
Each switch has two input/output terminals (Y
n
, Z
n
) and an
active HIGH enable input (E
n
). When E
n
is connected to
V
CC
, a low bidirectional path between Y
n
and Z
n
is
established (ON condition). When E
n
is connected to
ground (GND), the switch is disabled and a high
impedance between Y
n
and Z
n
is established (OFF
condition).
Current through a switch will not cause additional
V
CC
current provided the voltage at the terminals of the
switch is maintained within the supply voltage range;
V
CC
>> (V
Y
, V
Z
) >> GND. Inputs Y
n
and Z
n
are electrically
equivalent terminals.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
{ (C
L
+
C
S
)
×
V
CC2
×
f
o
} where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
{(C
L
+
C
S
)
×
V
CC2
×
f
o
} = sum of outputs
C
L
= output load capacitance in pF
C
S
= max. switch capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PZH
/ t
PZL
t
PHZ
/ t
PLZ
C
I
C
PD
C
S
turn “ON” time E
n
to V
OS
turn “OFF” time E
n
to V
OS
input capacitance
power dissipation capacitance per switch
max. switch capacitance
C
L
= 15 pF; R
L
= 1 k
;
V
CC
= 5 V
16
14
3.5
12
5
17
20
3.5
12
5
ns
ns
pF
pF
pF
notes 1 and 2
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