參數(shù)資料
型號: HCT373
廠商: System Logic Semiconductor Co., Ltd.
英文描述: Octal 3-State Noninverting Transparent Latch(High-Performance Silicon-Gate CMOS)
中文描述: 八路三態(tài)同相透明鎖存器(高性能硅柵CMOS)
文件頁數(shù): 4/5頁
文件大?。?/td> 52K
代理商: HCT373
SL74HCT373
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°
C to
-55
°
C
85
°
C
125
°
C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
28
35
42
ns
t
PLH
, t
PHL
Maximum Propagation Delay , Latch Enable to Q
(Figures 2 and 5)
32
40
48
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay ,Output Enable to Q
(Figures 3 and 6)
30
38
45
ns
t
PZL
, t
PZH
Maximum Propagation Delay , Output Enable to Q
(Figures 3 and 6)
35
44
53
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
12
15
18
ns
C
IN
Maximum Input Capacitance
10
10
10
pF
C
OUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
15
15
15
pF
Power Dissipation Capacitance (Per Latch)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
65
pF
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°
C to
-55
°
C
85
°
C
125
°
C
Unit
t
SU
Minimum Setup Time, Input D
to Latch Enable
(Figure 4)
10
13
15
ns
t
h
Minimum Hold Time,Latch
Enable to Input D
(Figure 4)
10
13
15
ns
t
w
Minimum Pulse Width, Latch
Enable (Figure 2)
12
15
18
ns
t
r,
t
f
Maximum Input Rise and Fall
Times (Figure 1)
500
500
500
ns
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