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參數(shù)資料
| 型號(hào)： | HCS373MS |
| 廠商： | Intersil Corporation |
| 英文描述： | Octal Transparent Latch, Three-State(抗輻射的八透明鎖存器（三態(tài)）) |
| 中文描述： | 八路透明鎖存器，三態(tài)（抗輻射的八透明鎖存器（三態(tài)）） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 183K |
| 代理商： | HCS373MS |
346
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCS373DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
20 Lead SBDIP
HCS373KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
20 Lead Ceramic Flatpack
HCS373D/Sample
+25
o
C
Sample
20 Lead SBDIP
HCS373K/Sample
+25
o
C
Sample
20 Lead Ceramic Flatpack
HCS373HMSR
+25
o
C
Die
Die
HCS373MS
Radiation Hardened
Octal Transparent Latch, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20
TOP VIEW
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
Q0
D0
D1
Q1
Q2
D3
D2
Q3
GND
VCC
D7
D6
Q6
Q7
Q5
D5
D4
Q4
LE
2
3
4
5
6
7
8
9
10
1
20
19
18
17
16
15
14
13
12
11
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
Features
3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-
Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCS373MS is a Radiation Hardened octal transpar-
ent three-state latch with an active-low output enable. The
HCS373MS utilizes advanced CMOS/SOS technology. The out-
puts are transparent to the inputs when the Latch Enable (LE) is
HIGH. When the Latch Enable (LE) goes LOW, the data is
latched. The Output Enable (OE) controls the three-state outputs.
When the Output Enable (OE) is HIGH, the outputs are in the
high impedance state. The latch operation is independent of the
state of the Output Enable.
The HCS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS373MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
September 1995
Spec Number
518845
File Number
2135.2
D
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|---|---|
| HCS373T | Radiation Hardened Octal Three-State Transparent Latch(抗輻射八透明鎖存器) |
| HCS373DTR | Radiation Hardened Octal Transparent Latch, Three-State |
| HCS373KTR | Radiation Hardened Octal Transparent Latch, Three-State |
| HCT04 | TRANSIENT SUPPRESSOR DIODE,SINGLE,UNIDIRECTIONAL,47.8V V(RWM),Axial-9.5 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCS373T | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal Transparent Latch, Three-State |
| HCS374D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered |
| HCS374D/SAMPLE | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered |
| HCS374DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered |
| HCS374HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered |
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