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參數(shù)資料
| 型號： | HCS193HMSR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Radiation Hardened Synchronous 4-Bit Up/Down Counter |
| 中文描述： | HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, UUC16 |
| 封裝： | DIE-16 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 158K |
| 代理商： | HCS193HMSR |
270
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCS193DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead SBDIP
HCS193KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
HCS193D/Sample
+25
o
C
Sample
16 Lead SBDIP
HCS193K/Sample
+25
o
C
Sample
16 Lead Ceramic Flatpack
HCS193HMSR
+25
o
C
Die
Die
HCS193MS
Radiation Hardened
Synchronous 4-Bit Up/Down Counter
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q1
Q0
CPD
CPU
Q2
GND
Q3
MR
TCD
TCU
PL
P2
P0
P1
VCC
P3
2
3
4
5
6
7
8
1
16
15
14
13
12
11
10
9
Q1
Q0
CPD
CPU
Q2
GND
Q3
P1
MR
TCD
TCU
PL
P2
P0
VCC
P3
Features
3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-
Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
- VIL = 0.30% VCC Max
- VIH = 0.70% VCC Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCS193MS is a Radiation Hardened 4-bit binary UP/
DOWN synchronous counter.
Presetting the counter to the number on the preset data inputs
(P0 - P3) is accomplished by a low on the asynchronous parallel
load input (PL). The counter is incremented on the low to high
transition of the clock-up input (high on the clock-down),
decremented on the low to high transition of the clock-down input
(high on the clock-up). A high level on the MR input overrides any
other input to clear the counter to zero. The Terminal Count Up
goes low half a clock period before the zero count is reached and
returns high at the maximum count.
The HCS193MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
September 1995
Spec Number
518759
File Number
3065.1
D
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCS193K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Synchronous 4-Bit Up/Down Counter |
| HCS193KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Synchronous 4-Bit Up/Down Counter |
| HCS193MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Synchronous 4-Bit Up/Down Counter |
| HCS195D/SAMPLE | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Inverting 8-Bit Parallel-Input/Serial Output Shift Register |
| HCS195DMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Inverting 8-Bit Parallel-Input/Serial Output Shift Register |
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