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參數(shù)資料
| 型號： | HCS125DMSR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Radiation Hardened Quad Buffer, Three-State |
| 中文描述： | HC/UH SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CDIP14 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-14 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 93K |
| 代理商： | HCS125DMSR |
123
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
HCS125MS
Radiation Hardened
Quad Buffer, Three-State
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
TOP VIEW
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
Functional Diagram
TRUTH TABLE
INPUTS
OUTPUT
An
OEn
Yn
H
L
H
L
L
L
X
H
Z
L = Low, H = High, X = Don’t Care, Z = High Impedance
OE1
A1
Y1
OE2
A2
Y2
GND
VCC
OE4
A4
Y4
OE3
A3
Y3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
14
13
12
11
10
9
8
2
3
4
5
6
7
1
OE1
A1
Y1
OE2
A2
Y2
GND
VCC
OE4
A4
Y4
OE3
A3
Y3
An
OEn
Yn
n
P
Features
3 Micron Radiation Hardened SOS CMOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day
(Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s, 20ns Pulse
Latch-Up Free Under Any Conditions
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
Input Current Levels Ii
≤
5
μ
A at VOL, VOH
Description
The Intersil HCS125MS is a Radiation Hardened quad three-state
buffer, each having its own output enable input. A high level on the
enable input puts the output in a high impedance state.
The HCS125MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS125MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE
SCREENING
LEVEL
PACKAGE
HCS125DMSR
-55
o
C to +125
o
C
Intersil Class
S Equivalent
14 Lead SBDIP
HCS125KMSR
-55
o
C to +125
o
C
Intersil Class
S Equivalent
14 Lead Ceramic
Flatpack
HCS125D/
Sample
+25
o
C
Sample
14 Lead SBDIP
HCS125K/
Sample
+25
o
C
Sample
14 Lead Ceramic
Flatpack
HCS125HMSR
+25
o
C
Die
Die
September 1995
Spec Number
518831
File Number
3559.1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCS125K | Radiation Hardened Quad Buffer, Three-State |
| HCS125HMSR | Radiation Hardened Quad Buffer, Three-State |
| HCS12COREUG | MC9S12DT128B |
| HCS132KMSR | Radiation Hardened Quad 2-Input NAND Schmitt Trigger |
| HCS132K | Radiation Hardened Quad 2-Input NAND Schmitt Trigger |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCS125HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad Buffer, Three-State |
| HCS125K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad Buffer, Three-State |
| HCS125KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad Buffer, Three-State |
| HCS125MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Quad Buffer, Three-State |
| HCS12BFAMILYPP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HCS12 B-Family Product Brief |
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