參數(shù)資料
型號： HCPL2400
英文描述： 20 MBd High CMR Logic Gate Optocouplers
中文描述： 20 MBd的高CMR邏輯門光電耦合器
文件頁數(shù)： 9/14頁
文件大?。?/td> 285K
代理商： HCPL2400
1-308
Package Characteristics
Parameter
Input-Output
Momentary
Withstand Voltage**
Input-Output
Resistance
Input-Output
Capacitance
Input-Input
Insulation Leakage
Current
Resistance
(Input-Input)
Capacitance
(Input-Input)
Sym.
V
ISO
Device
Min.
2500
Typ.*
Max.
Units
V rms
Test Conditions
RH
≤
50%,
t = 1 min.,
T
A
= 25
°
C
V
I-O
= 500 Vdc
Fig.
Note
3, 13
R
I-O
10
12
3
C
I-O
0.6
pF
f = 1 MHz
V
I-O
= 0 Vdc
RH
≤
45%
t = 5 s,
V
I-I
= 500 Vdc
V
I-I
= 500 Vdc
I
I-I
2430
0.005
μ
A
8
R
I-I
2430
10
11
8
C
I-I
2430
0.25
pF
f = 1 MHz
8
*
All typical values are at T
A
= 25
°
C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if
applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage,” publication number 5963-2203E.
Notes:
1. Each channel.
2. Duration of output short circuit time
not to exceed 10 ms.
3. Device considered a two terminal
device: pins 1, 2, 3, and 4 shorted
together, and pins 5, 6, 7, and 8
shorted together.
4. t
PHL
propagation delay is measured
from the 50% level on the rising edge
of the input current pulse to the 1.5 V
level on the falling edge of the output
pulse. The t
propagation delay is
measured from the 50% level on the
falling edge of the input current pulse
to the 1.5 V level on the rising edge of
the output pulse.
5. The typical data shown is indicative of
what can be expected using the
application circuit in Figure 13.
6. This specification simulates the worst
case operating conditions of the
HCPL-2400 over the recommended
operating temperature and V
range
with the suggested application circuit
of Figure 13.
7. Propagation delay skew is discussed
later in this data sheet.
8. Measured between pins 1 and 2
shorted together, and pins 3 and 4
shorted together.
9. Common mode transient immunity in a
Logic High level is the maximum
tolerable (positive) dV
CM
/dt of the
common mode pulse, V
CM
, to assure
that the output will remain in a Logic
High state (i.e., V
> 2.0 V. Common
mode transient immunity in a Logic
Low level is the maximum tolerable
(negative) dV
CM
/dt of the common
mode pulse, V
CM
, to assure that the
output will remain in a Logic Low state
(i.e., V
O
< 0.8 V).
10. Power Supply Noise Immunity is the
peak to peak amplitude of the ac ripple
voltage on the V
CC
line that the device
will withstand and still remain in the
desired logic state. For desired logic
high state, V
OH(MIN
) > 2.0 V, and for
desired logic low state,
V
< 0.8 V.
11. Use of a 0.1
μ
F bypass capacitor
connected between pins 8 and 5
adjacent to the device is required.
12. Peak Forward Input Current pulse
width < 50
μ
s at 1 KHz maximum
repetition rate.
13. In accordance with UL 1577, each
optocoupler is proof tested by applying
an insulation test voltage
≥
3000 V rms
for one second (leakage detection
current limit, I
≤
5
μ
A). This test is
performed before the 100% Produc-
tion test shown in the VDE 0884
Insulation Related Characteristics
Table, if applicable.
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