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參數(shù)資料
| 型號(hào)： | HCPL-193K-600 |
| 英文描述： | Dual Channel Line Receiver Dual Channel Line Receiver Dual Channel Line Receiver |
| 中文描述： | 雙通道線接收雙通道線接收雙通道線路接收器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 229K |
| 代理商： | HCPL-193K-600 |
7
Parameter
Symbol
Typ.
Units
Test Conditions
Fig.
Note
Resistance (Input-Output)
R
I-O
10
12
V
I-O
= 500 V dc
3, 13
Capacitance (Input-Output)
C
I-O
1.7
pF
f = 1 MHz
3, 13
Input-Input Insulation
Leakage Current
I
I-I
0.5
nA
45% Relative Humidity,
V
I-I
= 500 Vdc, t = 5 s
11
Resistance (Input-Input)
R
I-I
10
12
V
I-I
= 500 Vdc
11
Capacitance (Input-Input)
C
I-I
0.55
pF
f = 1 MHz
11
Propagation Delay Time of Enable
from V
EH
to V
EL
t
ELH
35
ns
6, 7
3, 7
R
= 510
, C
L
= 15 pF,
I
I
= 13 mA, V
EH
= 3 V, V
EL
= 0 V
Propagation Delay Time of Enable
from V
EL
to V
EH
t
EHL
35
ns
6, 7
3, 8
Output Rise Time (10-90%)
t
r
30
ns
3
R
L
= 510
, C
L
= 15 pF, I
I
= 13 mA
Output Fall Time (90-10%)
t
f
C
I
24
ns
3
Input Capacitance
60
pF
f = 1 MHz, V
= 0,
PINS 1 to 2 or 5 to 6
3
Typical Specifications
T
A
= 25
°
C, V
CC
= 5 V
Notes:
1. Bypassing of the power supply line is required, with a 0.1
μ
F ceramic disc capacitor adjacent to each isolator. The power supply bus
for the isolators should be separate from the bus for any active loads, otherwise additional bypass capacitance may be needed to
suppress regenerative feedback via the power supply.
2. Derate linearly at 1.2 mA/
°
C above T
A
= 100
°
C.
3. Each channel.
4. Device considered a two terminal device: pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together.
5. The t
propagation delay is measured form the 6.5 mA point on the trailing edge of the input pulse to the 1.5 V point on the trailing
edge of the output pulse.
6. The t
propagation delay is measured from the 6.5 mA point on the leading edge of the input pulse to the 1.5 V point on the leading
edge of the output pulse.
7. The t
enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point
on the trailing edge of the output pulse.
8. The t
enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point
on the leading edge of the output pulse.
9. CM
H
is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state, i.e.
V
> 2.0 V.
10. CM
L
is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state, i.e.
V
< 0.8 V.
11. Measured between adjacent input leads shorted together, i.e. between 1, 2 and 4 shorted together and pins 5, 6 and 8 shorted
together.
12. No external pull up is required for a high logic state on the enable input.
13. Measured between pins 1 and 2 or 5 and 6 shorted together, and pins 10 through 15 shorted together.
14. Parameters shall be tested as part of device initial characterization and after process changes. Parameters shall be guaranteed to the
limits specified for all lots not specifically tested.
15. Standard parts receive 100% testing at 25
°
C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25, 125, and -55
°
C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
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