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| 型號： | HCPL-0731V |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 光電耦合器 |
| 英文描述： | LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS |
| 中文描述： | 2 CHANNEL LOGIC OUTPUT OPTOCOUPLER |
| 封裝： | SO-8 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 280K |
| 代理商： | HCPL-0731V |
12/11/03
Page 4 of 12
2003 Fairchild Semiconductor Corporation
LOW INPUT CURRENT
HIGH GAIN SPLIT
DARLINGTON OPTOCOUPLERS
SINGLE CHANNEL:
DUAL CHANNEL:
HCPL-0700
HCPL-0730
HCPL-0701
HCPL-0731
NOTES
1. Current Transfer Ratio is de
fi
ned as a ratio of output collector current, I
2. Pin 7 open. Use of a resistor between pins 5 and 7 will decrease gain and delay time.
3. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV
common mode pulse signal, V
CM
, to assure that the output will remain in a logic high state (i.e., V
O
>2.0 V). Common mode
transient immunity in logic low level is the maximum tolerable (negative) dV
CM
/dt on the trailing edge of the common mode
pulse signal, V
CM
, to assure that the output will remain in a logic low state (i.e., V
O
<0.8 V).
4. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.
5. 2500 VAC RMS for 1 minute duration is equivalent to 3000 VAC RMS for 1 second duration.
** All typicals at TA = 25
°
C
O
, to the forward LED input current, I
F
, times 100%.
CM
/dt on the leading edge of the
SWITCHING CHARACTERISTICS
(T
A
= 0 to 70
°
C unless otherwise speci
fi
ed., V
CC
= 5 V)
Parameter
Test Conditions
Symbol
Device
Min
Typ**
Max
Unit
Propagation delay
time to logic low
(Note 2) (Fig. 14)
(R
L
= 4.7 k
, I
F
= 0.5 mA)
T
PHL
HCPL-0701
HCPL-0731
HCPL-0701
HCPL-0731
HCPL-0701
HCPL-0731
HCPL-0701
HCPL-0731
HCPL-0700
HCPL-0730/0731
HCPL-0700
HCPL-0730/0731
HCPL-0701/31
HCPL-0701/31
HCPL-0701
HCPL-0731
HCPL-0701
HCPL-0731
HCPL-0700/30/31
HCPL-0700/30/31
30
120
25
100
2
3
1
2
15
25
10
20
90
60
10
15
7
10
50
35
μs
T
A
= 25
°
C
3
5
(R
L
= 270
, I
F
= 12 mA)
T
A
= 25
°
C
0.3
0.4
(R
L
= 2.2 k
, I
F
= 1.6 mA)
T
A
= 25
°
C
1
2
Propagation delay
time to logic high
(Note 2) (Fig. 14)
(R
L
= 4.7 k
, I
F
= 0.5 mA)
T
PLH
μs
T
A
= 25
°
C
12
(R
L
= 270
, I
F
= 12 mA)
T
A
= 25
°
C
1.6
1.6
(R
L
= 2.2 k
, I
F
= 1.6 mA)
T
A
= 25
°
C
7
Common mode
transient
immunity at
logic high
Common mode
transient
immunity at
logic low
(I
F
= 0 mA, |V
CM
| = 10 V
P-P
)
T
A
= 25
°
C (R
L
= 2.2 k
) (Note 3) (Fig. 15)
|CM
H
|
ALL
1,000
10,000
V/μs
(I
F
= 1.6 mA, |V
CM
| = 10 V
P-P
,
R
L
= 2.2 k
)
T
A
= 25
°
C (Note 3) (Fig. 15)
|CM
L
|
ALL
1,000
10,000
V/μs
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