參數(shù)資料
型號(hào): HCPL-0201
英文描述: Very High CMR, Wide VCC Logic Gate Optocouplers(非常高的共態(tài)抑制,寬范圍電壓的邏輯門光耦器)
中文描述: 非常高CMR,寬虛擬通道連接邏輯門光電耦合器(非常高的共態(tài)抑制,寬范圍電壓的邏輯門光耦器)
文件頁(yè)數(shù): 11/16頁(yè)
文件大?。?/td> 266K
代理商: HCPL-0201
11
Package Characteristics
Parameter
Input-Output Momentary
Withstand
Voltage
*
Sym.
V
ISO
Min. Typ. Max. Units
2500
5000
Test Conditions
Fig.
Note
5, 10
5, 11
V rms RH < 50%, t = 1 min.
T
A
= 25
°
C
HCNW22XX
Input-Output Resistance
R
I-O
10
12
10
13
V
I-O
= 500 Vdc
5
HCNW22XX
10
12
10
11
T
A
= 25
°
C
T
A
= 100
°
C
Input-Output Capacitance
C
I-O
0.6
0.5
0.005
pF
f = 1 MHz,
V
I-O
= 0 Vdc
5
HCNW22XX
0.6
T
A
= 25
°
C
Relative Humidity = 45%,
t = 5 s, V
I-I
= 500 V
V
I-I
= 500 V
f = 1 MHz
Input-Input Insulation
Leakage Current
Resistance (Input-Input)
Capacitance (Input-Input)
I
I-I
μ
A
12
R
I-I
C
I-I
10
11
0.25
pF
12
12
*
The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable),
your equipment level safety specification or Agilent Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,”
publication number 5963-2203E.
Notes:
1. Each channel.
2. Derate total package power dissipation, P
T
, linearly above 70
°
C free-air temperature at a rate of 4.5 mW/
°
C.
3. Duration of output short circuit time should not exceed 10 ms.
4. For single devices, input capacitance is measured between pin 2 and pin 3.
5. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
6. The t
PLH
propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the
leading edge of the output pulse. The t
PHL
propagation delay is measured from the 50% point on the trailing edge of the input
pulse to the 1.3 V point on the trailing edge of the output pulse.
7. CM
H
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state,
V
O
> 2.0 V. CM
L
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic
low state, V
O
< 0.8 V.
8. For HCPL-2202/12, V
O
is on pin 6.
9. Use of a 0.1
μ
F bypass capacitor connected between pins 5 and 8 is recommended.
10. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
3000 V rms for one second
(leakage detection current limit, I
I-O
5
μ
A). This test is performed before the 100% production test for partial discharge (Method
b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.
11. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage
6000 V rms for one second
(leakage detection current limit, I
I-O
5
μ
A). This test is performed before the 100% production test for partial discharge (Method
b) shown in the VDE 0884 Insulation Characteristics Table.
12. For HCPL-2231/32 only. Measured between pins 1 and 2, shorted together, and pins 3 and 4, shorted together.
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PDF描述
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