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參數(shù)資料
| 型號(hào)： | HCF4046M013TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | MICROPOWER PHASE-LOCKED LOOP |
| 中文描述： | 微功耗鎖相環(huán) |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 686K |
| 代理商： | HCF4046M013TR |
HCF4046B
2/12
VCO Section
The VCO requires one external capacitor C1 and
one or two external resistors (R1 or R1 and R2).
Resistor R1 and capacitor C1 determine the
frequency range of the VCO and resistor R2
enables the VCO to have a frequency offset if
required. The high input impedance (10
12
) of the
VCO simplifiers the design of low-pass filters by
permitting the designer a wide choice of
resistor-to-capacitor ratios. In order not to load the
low-pass filter, a source-follower output of the
VCO input voltage is provided at terminal 10
(DEMODULATED OUTPUT). If this terminal is
used, a load resistor (R
S
) of 10 K
or more should
be connected from this terminal to V
SS
. If unused
this terminal should be left open. The VCO can be
connected either directly or through frequency
dividers to the comparator input of the phase
comparators. A full CMOS logic swing is available
at the output of the VCO and allows direct
coupling to CMOS frequency dividers such as the
HCF4024B, HCF4018B, HCF4020B, HCF4022B,
HCF4029B and HBF4059A. One or more
HCF4018B (Presettable Divide-by-N Counter) or
HCF4029B (Presettable Up/Down Counter), or
HBF4059A
(Programmable
Counter),
together
with
(Phase-Locked Loop) can be used to build a
micropower low-frequency synthesizer. A logic 0
on the INHIBIT input "enables" the VCO and the
source follower, while a logic 1 "turns off" both to
minimize stand-by power consumption.
Divide-by-"N"
HCF4046B
the
Phase Comparators
The phase-comparator signal input (terminal 14)
can be direct-coupled provided the signal swing is
within CMOS logic levels [logic "0"
≤
30% of
(V
DD
-V
SS
), logic "1"
≥
70% of (V
DD
-V
SS
)]. For
smaller swings the signal must be capacitively
coupled to the self-biasing amplifier at the signal
input. Phase comparator I is an exclusive-OR
network; it operates analagously to an over-driven
balanced mixer. To maximize the lock range, the
signal-and comparator-input frequencies must
have a 50% duty cycle. With no signal or noise on
the signal input, this phase comparator has an
average output voltage equal to V
DD
/2. The
low-pass filter connected to the output of phase
comparator I supplies the averaged voltage to the
VCO input, and causes the VCO to oscillate at the
center frequency (fo). The frequency range of
input signals on which the PLL will lock if it was
initially out of lock is defined as the frequency
capture range (2 f
C
). The frequency range of input
signals on which the loop will stay locked if it was
initially in lock is defined as the frequency lock
range (2 f
L
). The capture range is
≤
the lock range.
With phase comparator I the range of frequencies
over which the PLL can acquire lock (capture
range) is dependent on the low-pass-filter
characteristics, and can be made as large as the
lock range. Phase-comparator I enables a PLL
system to remain in lock in spite of high amounts
of noise in the input signal. One characteristic of
this type of phase comparator is that it may lock
onto input frequencies that are close to harmonics
of
the
VCO
center-frequency.
characteristic is that the phase angle between the
signal and the comparator input varies between 0°
and 180°, and is 90° at the center frequency. Fig.1
shows the typical, triangular, phase-to-output
response characteristic of phase-comparator I.
Typical
waveforms
phase-locked-loop employing phase comparator I
in locked condition of fo is shown in fig.2.
Phase-comparator II is an edge-controlled digital
memory network. It consists of four flip-flop
stages, control gating, and a three-stage
output-circuit comprising p- and n-type drivers
having a common output node. When the p-MOS
or n-MOS drivers are ON they pull the output up to
V
DD
or down to V
SS
, respectively. This type of
phase comparator acts only on the positive edges
of the signal and comparator inputs. The duty
cycles of the signal and comparator inputs are not
important since positive transitions control the PLL
system utilizing this type of comparator. If the
signal-input frequency is higher than the
comparator-input frequency, the p-type output
driver is maintained ON most of the time, and both
the n- and p-drivers OFF (3 state) the remainder of
the time. If the signal-input frequency is lower than
the comparator-input frequency, the n-type output
driver is maintained ON most of the time, and both
the n- and p-drivers OFF (3 state) the remainder of
the time. If the signal and comparator-input
frequencies are the same, but the signal input lags
the comparator input in phase, the n-type output
driver is maintained ON for a time corresponding
to the phase difference. If the signal and
comparator-input frequencies are the same, but
the comparator input lags the signal in phase, the
A
second
for
a
CMOS
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| HCC4047BF | LOW-POWELOW-POWER MONOSTABLE/ASTABLE MULTIVIBRATOR |
| HCF4047B | LOW-POWELOW-POWER MONOSTABLE/ASTABLE MULTIVIBRATOR |
| HCF4047BEY | LOW-POWELOW-POWER MONOSTABLE/ASTABLE MULTIVIBRATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCF4047 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW-POWER MONOSTABLE/ASTABLE MULTIVIBRATOR |
| HCF4047B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW-POWELOW-POWER MONOSTABLE/ASTABLE MULTIVIBRATOR |
| HCF4047BC1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW-POWELOW-POWER MONOSTABLE/ASTABLE MULTIVIBRATOR |
| HCF4047BEY | 功能描述:單穩(wěn)態(tài)多諧振蕩器 Mono/Astable Mutlivi RoHS:否 制造商:Texas Instruments 每芯片元件:1 邏輯系列:LVC 邏輯類型:Monostable Multivibrator 封裝 / 箱體:SSOP-8 傳播延遲時(shí)間:18.6 ns 高電平輸出電流:- 32 mA 低電平輸出電流:32 mA 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| HCF4047BF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Monostable Multivibrator |
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