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參數資料
| 型號： | HCF4046BEY |
| 廠商： | 意法半導體 |
| 英文描述： | MICRMICROPOWER PHASE-LOCKED LOOP _ |
| 中文描述： | MICRMICROPOWER鎖相環(huán)_ |
| 文件頁數： | 2/13頁 |
| 文件大?。?/td> | 239K |
| 代理商： | HCF4046BEY |
VCO Section
The VCO requires one external capacitor C1 and
one ortwoexternal resistors(R1orR1and R2).Re-
sistorR1 andcapacitorC1determine the frequency
range of the VCO and resistor R2enables theVCO
to have a frequency offsetif required. The high input
impedance (10
12
) oftheVCOsimplifiersthedesign
of low-pass filters by permitting the designer a wide
choice of resistor-to-capacitor ratios. In order not to
loadthelow-passfilter,asource-follower outputofthe
VCO input voltage is provided at terminal 10 (DE-
MODULATED OUTPUT). If this terminal is used, a
load resistor (R
S
) of 10 k
or more should be con-
nected fromthis terminal to V
SS
. Ifunused this termi-
nal should be left open. TheVCOcanbe connected
either directly or through frequency dividers to the
comparator input of the phase comparators. A full
COS/MOSlogicswingis available attheoutputofthe
VCO and allows direct coupling to COS/MOS fre-
quency dividers such as the
HCC/HCF4024B
,
HCC/HCF4018B
,
HCC/HCF4020B
,
HCC/HCF4022B
,
HCC/HCF4029B
,and
HBC/HBF4059A
. One or more
HCC/HCF4018B
(Presettable Divide-by-N Counter) or
HCC/HCF4029B
(Presettable Up/Down Counter), or
HBC/HBF4059A
(Programmable Divide-by-”N” Counter), together
withthe
HCC/HCF4046B
(Phase-Locked Loop)can
be used to build a micropower low-frequency syn-
thesizer.Alogic 0ontheINHIBITinput ”enables” the
VCO and the source follower, while a logic 1 ”turns
off” both to minimize stand-by power consumption.
Phase Comparators
The phase-comparator signal input (terminal 14)
can be direct-coupled provided the signal swing is
within COS/MOS logic levels [logic ”0”
≤
30 %
(V
DD
– V
SS
), logic ”1”
≥
70 % (V
DD
- V
SS
)]. For
smaller swings the signal must be capacitively
coupled to the self-biasing amplifier at the signal
input. Phase comparator I is an exclusive-OR net-
work;it operates analagously toanover-driven bal-
anced mixer. To maximize the lock range, the
signal-and comparator-input frequencies musthave
a 50%duty cycle.Withno signal ornoise on the sig-
nal input, this phase comparator has an average
output voltage equal to V
DD
/2. The low-pass filter
connected to the output of phase comparator Isup-
plies the averaged voltage to the VCO input, and
causes theVCO to oscillate at thecenter frequency
(f
o
). The frequency range of input signals on which
the PLLwilllock ifitwas initiallyoutof lockis defined
as thefrequency capture range (2f
c
).Thefrequency
range of input signals on which the loop will stay
locked if it was initially in lock is defined as the fre-
quencylockrange (2 f
L
). The capture range is
≤
the
lock range. With phase comparator I the range of
frequencies over which the PLL can acquire lock
(capture range) is dependent on the low-pass-filter
characteristics, and can be made as large as the
lock range. Phase-comparator I enables aPLL sys-
tem to remain in lock in spite of high amounts of
noise in the input signal. One characteristic of this
type of phase comparator is that it may lock onto
input frequencies that are close to harmonics of the
VCO center-frequency. A second characteristic is
that the phase angle between the signal and the
comparator input varies between 0
°
and 180
°
, and
is 90
°
at the center frequency. Fig. (a) shows the
typical, triangular, phase-to-output response char-
acteristicofphase-comparator I.Typical waveforms
for a COS/MOS phase-locked-loop
phasecomparator Iinlocked conditionoff
o
isshown
infig. (b).Phase-comparator II isanedge-controlled
digital memory network. It consists of four flip-flop
stages, control gating, and a three-stage output-cir-
cuit comprising p-and n-type drivers having a com-
mon output node. When the p-MOS or n-MOS
driversareONtheypull theoutputuptoV
DD
ordown
to V
SS
, respectively. This type of phase comparator
acts only on the positive edges of the signal and
comparator inputs. Thedutycyclesofthesignaland
comparator inputs are not important since positive
transitions control the PLL system utilizing this type
of comparator. Ifthesignal-input frequency ishigher
than the comparator-input frequency, the p-type
outputdriver ismaintainedONmost ofthetime,and
both the n- and p-drivers OFF (3 state) the remain-
der of thetime.If the signal-input frequency is lower
than the comparator-input frequency, the n-type
outputdriver ismaintainedONmost ofthetime,and
both the n- and p-drivers OFF (3 state) the remain-
der of the time. If the signal and comparator-input
frequencies are the same, but the signalinput lags
the comparator input in phase, the n-type output
driver is maintained ONfor a time corresponding to
the phase difference. If the signal and comparator-
input frequencies are thesame, butthecomparator
input lags the signal in phase, the p-type output
driver is maintained ONfor a time corresponding to
the phase difference. Subsequently, the capacitor
voltageofthelow-passfilterconnected tothisphase
comparator is adjusted until the signal and com-
parator inputs are equal in both phase and fre-
quency. Atthisstablepoint both p-andn-type output
drivers remain OFFand thus the phase comparator
output becomes an open circuit and holds the volt-
age on the capacitor of the low-pass filter constant.
Moreover the signal at the”phase pulses” output is
a highlevelwhich canbe usedforindicating alocked
condition. Thus, for phase comparator II, no phase
difference exists between signal and comparator
employing
HCC/HCF4046B
2/13
相關PDF資料 |
PDF描述 |
|---|---|
| HCC4046BF | MICRMICROPOWER PHASE-LOCKED LOOP _ |
| HCF4046BC1 | Analog Phase-Locked Loop |
| HCC4049BF | HEX BUFFER/CONVERTERS |
| HCF4049BC1 | HEX BUFFER/CONVERTERS |
| HCF4049BEY | HEX BUFFER/CONVERTERS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HCF4046BF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Phase-Locked Loop |
| HCF4046BM1 | 功能描述:鎖相環(huán) - PLL PHASE-LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| HCF4046M013TR | 功能描述:鎖相環(huán) - PLL MICROPwr PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| HCF4047 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW-POWER MONOSTABLE/ASTABLE MULTIVIBRATOR |
| HCF4047B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW-POWELOW-POWER MONOSTABLE/ASTABLE MULTIVIBRATOR |
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