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參數(shù)資料
| 型號： | HCF40105 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | FIFO REGISTER |
| 中文描述： | FIFO寄存器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 260K |
| 代理商： | HCF40105 |
LOADINGDATA
Datacan be entered whenever theDATA-IN READY
(DIR) flag is high, by a low to high transition on the
SHIFT-IN(SI) input. This input must go lowmomen-
tarily before the next word is accepted by the FIFO.
The DIR flag will go low momentarily, until the data
havebeen transferred tothesecondlocation.The flag
will remain low when all 16-word locations are filled
with valid data, and further pulses on theSIinput will
be ignored until DIR goes high.
UNLOADINGDATA
As soon as the first word has rippled to the output,
DATA-OUT READY (DOR) goes high, and data can
beremovedbyafalling edgeontheSOinput.Thisfall-
ing edge causes the DORsignal to go low while the
word on the output is dumped and the next word
moves to theoutput. As long as valid data are avail-
ableintheFIFO,theDORsignal willgohigh again sig-
nifyingthatthe nextwordisreadyatthe output.When
theFIFO isempty, DOR will remain low, and any fur-
ther commands will be ignored until a ”1” marker
ripples down to the last control register, when DOR
goes high. Unloading of data is inhibited while the 3-
statecontrol input is high. The 3-state control signal
should not be shifted from high to low (data outputs
turnedon)while theSHIFT-OUTisatlogic0.Thislevel
change would cause the first word to be shifted out
(unloaded) immediately and the data to be lost.
CASCADING
The
HCC/HCF40105B
can be cascaded to form
longer registers simply by connecting the DIRto SO
and DOR to SI. In the cascaded mode, a MASTER
RESETpulsemustbeapplied afterthesupplyvoltage
isturned on. Forwords wider than 4 bits, the DIR and
the DOR outputs must be gated together with AND
gates. Their outputsdrivethe SIand SOinputsinpar-
allel, if expanding is done in both directions.
3-STATE OUTPUTS
In order to facilitate data busing, 3-state outputs are
provided on the data outputlines, whiletheload con-
dition of the register can be detected by the state of
theDORoutput.
MASTERRESET
Ahigh on theMASTER RESET (MR) setsall the con-
trol logic marker bits to ”0”. DOR goes low and DIR
goes high. The contents of the data register are not
changed, only declared invalid, and will be super-
seded when the first word isloaded.
APPLICATIONS INFORMATION
EXPANSION, 8 BITS–WIDE–BY–16 N–BITS LONG.
HCC/HCF40105B
8/12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCF40105BEY | FIFO REGISTER |
| HCC40106B | Darlington Bipolar Transistor; Package/Case:TO-3; Current Rating:8A; Voltage Rating:80V |
| HCF40106M013TR | HEX SCHMITT TRIGGERS |
| HCC40106BF | Darlington Bipolar Transistor; Mounting Type:Through Hole; Package/Case:TO-3; Current Rating:10A; Voltage Rating:80V RoHS Compliant: Yes |
| HCF40106BEY | Quadruple Differential Line Receiver 16-SOIC 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCF40105B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:FIFO REGISTER |
| HCF40105BC1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:FIFO REGISTER |
| HCF40105BEY | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:FIFO REGISTER |
| HCF40105BF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Asynchronous FIFO |
| HCF40106 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HEX SCHMITT TRIGGERS |
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