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參數(shù)資料
| 型號： | HCF40104BEY |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| 中文描述： | 4位雙向通用移位寄存器 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 270K |
| 代理商： | HCF40104BEY |
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
*
Parameter
Value
Unit
V
V
V
mA
mW
Supply Voltage :
HCC
Types
HCF
Types
– 0.5 to + 20
– 0.5 to + 18
– 0.5 to V
DD
+ 0.5
±
10
200
V
i
I
I
P
tot
Input Voltage
DC Input Current (any one input)
Total Power Dissipation (per package)
Dissipation per Output Transistor
for T
op
= Full Package-temperature Range
Operating Temperature :
HCC
Types
100
mW
°
C
°
C
°
C
T
op
HCF
Types
– 55 to + 125
– 40 to + 85
– 65 to + 150
T
stg
Storage Temperature
RECOMMENDED OPERATING CONDITIONS
Symbol
V
DD
Parameter
Value
3 to 18
3 to 15
0 to V
DD
– 55 to + 125
– 40 to + 85
Unit
V
V
V
°
C
°
C
Supply Voltage :
HCC
Types
HCF
Types
V
I
Input Voltage
Operating Temperature :
HCC
Types
T
op
HCF
Types
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltages are with respect to V
SS
(GND).
JAM inputs is asynchronously forced into the
counter regardless of the state of the SPE, CI/CE,
or CLOCK inputs. JAM inputs JO-J7 represent two
4-bit BCD words for the
HCC/HCF40102B
and a
single 8-bit binary word for the
HCC/HCF40103B
.
When the CLEAR (CLR) input is low, the counter
is asynchronously cleared to its maximum count
(99
10
for the
HCC/HCF40102B
and 255
10
for
the
HCC/HCF40103B)
regardless of the state of
any other input. The precedence relationship be-
tween control input is indicated in thetruth table. If
all control inputs are high at thetiemeof zerocount,
the counters will jump to themaximum count, giving
a counting sequence of 100 or 256 clock pulses
long. The
HCC/HCF40102B
and
HCC/HCF40103B
may be cascaded using the CI/CE input and the
HCC/HCF40102B/40103B
2/13
相關(guān)PDF資料 |
PDF描述 |
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| HCF40104BF | 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| HCF40194BEY | Quadruple Differential Line Receiver 16-SO 0 to 70 |
| HCF40194BF | Quadruple Differential Line Receiver 16-SO 0 to 70 |
| HCC40102BF | Synchronous Down Counter |
| HCC40103BF | Synchronous Down Counter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCF40104BF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| HCF40105 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:FIFO REGISTER |
| HCF40105B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:FIFO REGISTER |
| HCF40105BC1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:FIFO REGISTER |
| HCF40105BEY | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:FIFO REGISTER |
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