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參數(shù)資料
| 型號(hào)： | HCD66731A01BP |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display |
| 中文描述： | 點(diǎn)陣液晶顯示控制器/驅(qū)動(dòng)器支持日語(yǔ)漢字，韓文字體顯示 |
| 文件頁(yè)數(shù)： | 86/131頁(yè) |
| 文件大?。?/td> | 5332K |
| 代理商： | HCD66731A01BP |
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HD66730/HD66731
85
Receiving (write)
After receiving the start synchronizing bit string, the R/W bit (= 0), and the RS bit in the start byte, an
8-bit instruction is received in 2 bytes: the lower 4 bits of the instruction are placed in the LSB of the
first byte, and the higher 4 bits of the instruction are placed in the LSB of the second byte. Be sure to
transfer 0 in the following 4 bits of each byte. When instructions are received with R/W bit and RS bit
unchanged, continuous transfer is possible (see Continuous Transfer in the following).
Transmitting (read)
After receiving the synchronizing bit string, the R/W bit (= 0), and the RS bit in the start byte, 8-bit read
data is transmitted from pin SOD in the same way as receiving. When read data is transmitted with R/W
bit and RS bit unchanged, continuous transfer is possible (see Continuous Transfer in the following).
The status register (SR) is read when the RS bit is 0. RAM data is read out when the RS bit is set to 1
after designating RAM data register (R9) with the index register (IR). Bits RM1/0 of entry mode
register (R0) select the RAM. When reading RAM data, an interval longer than the RAM reading time
must be taken after the start byte has been accepted and before the first data has been read out. During
transmission (data output), the SID input is continuously monitored for a start synchronizing bit string
(11111). Once this has been detected, the R/
W
and RS bits are received. Accordingly, 0 must always be
input to SID when transmitting data continuously.
Continuous Transfer
When instructions are received with the R/W bit and RS bit unchanged, continuous receive is possible
without inserting a start byte between instructions.
After receiving the last bit (the 8th bit in the 2nd byte) of an instruction, the system begins to execute it.
To execute the next instruction, the instruction execution time of the HD66730/1 must be considered. If
the last bit (the 8th bit in the 2nd byte) of the next instruction is received during execution of the
previous instruction, the instruction will be ignored.
In addition, if the next unit of data is read before read execution of previous data is completed for RAM
data, normal data is not sent. To transfer data normally, the busy flag must be checked. However, if the
amount of wiring used for transmission needs to be reduced, or if the burden of polling on the CPU
needs to be lightened, transfer can be performed without reading the busy flag. In this case, insert a
transfer wait between instructions so that the current instruction has time to complete execution. Figure
21 shows the procedure for continuous data transfer.
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