參數(shù)資料
型號(hào)： HCD66717A03BP
廠商： Hitachi,Ltd.
元件分類： 晶體
英文描述： (Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver)
中文描述： （低功耗點(diǎn)陣液晶顯示控制器/驅(qū)動(dòng)器）
文件頁(yè)數(shù)： 43/90頁(yè)
文件大?。?/td> 716K
代理商： HCD66717A03BP
HD66717
495
Transferring Serial Data
I
2
C Bus Interface
Grounding the IM1 and IM0 pins (interface mode pins) allows serial data transfer conforming to the I
bus interface over the serial data line (SDA) and serial transfer clock line (SCL). Here, the HD66717
operates in an exclusive-receive slave mode.
2
C
The HD66717 initiates serial data transfer by transferring the first byte when a high SCL level at the
falling edge of the SDA input is sampled; it ends serial data transfer when a high SCL level at the rising
edge of the SDA input is sampled.
The HD66717 is selected when the higher six bits of the 7-bit slave address in the first byte transferred
from the master device match the 6-bit device identification code assigned to the HD66717. The
HD66717, when selected, receives the subsequent data strings. Any identification code can be assigned
by the DB5/ID5 to DB0/ID0 pins; select an appropriate code that is not assigned to any other slave
device. The higher four bits (ID5 to ID2) of this identification code is recommended as 0111. Two
different slave addresses must be assigned to a single HD66717 because the least significant bit (LSB) of
the slave address is used as a register select bit (RS): when RS = 0, an instruction can be issued and when
RS = 1, data can be written to a RAM. The eighth bit of the first byte (R/W bit) must be 0 since the
HD66717 exclusively receives data.
The ninth bit of the first byte is a receive-data acknowledge bit (ACK). When the received slave address
matches the device ID code, the HD66717 pulls down the ACK bit to a low level. Therefore, the ACK
output buffer is an open-drain structure, only allowing low-level output. However, the ACK bit is
undetermined immediately after power-on; make sure to initialize the LSI using the RESET* input.
After identifying the address in the first byte, the HD66717 receives the subsequent data as an HD66717
instruction or as RAM data. Having received 8-bit data normally, the HD66717 pulls down the ninth bit
(ACK) to a low level. Therefore, if the ACK is not returned, the data must be transferred again. Multiple
bytes of data can be consecutively transferred until the transfer-end condition is satisfied. Here, when the
serial data transfer rate is longer than that of the HD66717 instruction execution cycle, effective data
transfer is possible without retransmission (see Table 17, Instruction List). Note that the display-clear
instruction alone requires longer execution time than the others.
Table 18 illustrates the first bytes of I
timing sequence .
2
C bus interface data and Figure 22 shows the I
2
C bus interface
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