參數(shù)資料
型號： HCD66717A03
廠商： Hitachi,Ltd.
元件分類： 晶體
英文描述： (Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver)
中文描述： （低功耗點陣液晶顯示控制器/驅(qū)動器）
文件頁數(shù)： 4/90頁
文件大小： 716K
代理商： HCD66717A03
HD66717
455
LCD-II Family Comparison (cont)
Item
Power supply voltage
Liquid crystal drive voltage 3.0 to 11.0V
Maximum display
characters per chip
HD66720
2.7V to 5.5V
HD66717
2.4V to 5.5V
3.0 to 13.0V
12 characters
×
1 line/2 lines/3 lines/4 lines
HD66727
2.4V to 5.5V
3.0 to 13.0V
12 characters
×
1 line/2 lines/3 lines/4 lines
10 characters
×
1 line/
8 characters
×
2 lines
42 (extended to 80)
1/9 and 1/17
9,600 bits
(240 5-
×
-8 dot
characters)
64 bytes
40 bytes
16 bytes
42
17
B
Segment display
Display duty ratio
CGROM
40 (and 10 annunciators)
1/10, 1/18, 1/26, and 1/34
9,600 bits
(240 5-
×
-8 dot
characters)
32 bytes
60 bytes
8 bytes
60
34
B
40 (and 12 annunciators)
1/10, 1/18, 1/26, and 1/34
11,520 bits
(240 6-
×
-8 dot
characters)
32 bytes
60 bytes
8 bytes
60
34
B
CGRAM
DDRAM
SEGRAM
Segment signals
Common signals
Liquid crystal drive
waveform
Clock source
External resistor
or external clock
160 kHz ± 30%
External resistor
or external clock
1-line mode: 40 kHz ± 30%
2-line mode: 80 kHz ± 30%
3-line mode: 120 kHz ± 30%
4-line mode: 160 kHz ± 30%
Double or triple
booster circuit
Built-in for each V1 to V5
External resistor
or external clock
1-line mode: 40 kHz ± 30%
2-line mode: 80 kHz ± 30%
3-line mode: 120 kHz ± 30%
4-line mode: 160 kHz ± 30%
Double or triple
booster circuit
Built-in for each V1 to V5
Rf oscillation frequency
Liquid crystal voltage
booster circuit
Liquid crystal drive
operational amplifier
Bleeder-resistor for liquid
crystal drive
Liquid crystal contrast
adjuster
Key scan circuit
Extension driver control
signal
Reset function
Double or triple
booster circuit
None
External
Internal 1/4 and 1/6 bias
resistors
Incorporated
Internal 1/4 and 1/6 bias
resistors
Incorporated
None
5
×
6 = 30 keys
Independent
control signal
Internal reset
circuit or reset input
Dot unit and
line unit
Impossible
1 or 2
Low power mode and sleep
mode
Serial
100-pin QFP1420
100-pin TQFP1414
100-pin bare chip
None
None
4
×
8 = 32 keys
None
Reset input
Reset input
Horizontal smooth scroll
Impossible
Impossible
Vertical smooth scroll
Number of displayed lines
Low power control
Dot (raster-row) unit
1, 2, 3, or 4
Standby mode and
sleep mode
I
Slim chip with/without bumps
TCP
Dot (raster-row) unit
1, 2, 3, or 4
Standby mode and
sleep mode
I
Slim chip with/without bumps
TCP
Bus interface
Package
2
C, serial, 4, or 8 bits
2
C or clock-synchronized serial
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