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參數(shù)資料
| 型號： | HCD61202U |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Dot Matrix Liquid Crystal GraphicDisplay Column Driver |
| 中文描述： | 點(diǎn)陣液晶GraphicDisplay列驅(qū)動器 |
| 文件頁數(shù)： | 8/33頁 |
| 文件大小： | 197K |
| 代理商： | HCD61202U |
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HD61202U
823
Terminal
Name
Number of
Terminals
I/O
Connected to
Functions
ADC
1
I
V
CC
/GND
Address control signal to determine the relation between
Y address of display RAM and terminals from which the
data is output.
ADC = High: Y1: H’0, Y64: H’63
ACD = Low: Y64: H’0, Y1: H’63
DB0–DB7
8
I/O
MPU
Data bus, three-state I/O common terminal.
M
1
I
HD61203U
Switch signal to convert liquid crystal drive waveform
into AC.
FRM
1
I
HD61203U
Display synchronous signal (frame signal).
Presets the 6-bit display line counter and synchronizes
the common signal with the frame timing when the FRM
signal becomes high.
CL
1
I
HD61203U
Synchronous signal to latch display data. The rising CL
signal increments the display output address counter
and latches the display data.
1, 2
2
I
HD61203U
2-phase clock signal for internal operation.
The 1 and 2 clocks are used to perform operations
(I/O of display data and execution of instructions) other
than display.
Y1–Y64
64
O
Liquid crystal
display
Liquid crystal display column (segment) drive output.
The outputs at these pins are at the light-on level when
the display RAM data is 1, and at the light-off level when
the display RAM data is 0.
Relation among output level, M, and display data (D) is
as follows:
M
D
Output
level
1
0
1
0
1
0
V1 V3 V2 V4
567
1
I
MPU or
external CR
The following registers can be initialized by setting the
567
signal to low level.
1. On/off register 0 set (display off)
2. Display start line register line 0 set (displays from line
0)
After releasing reset, this condition can be changed only
by instruction.
NC
3
Open
Unused terminals. Don’t connect any lines to these
terminals.
Note: 1 corresponds to high level in positive logic.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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