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參數(shù)資料
| 型號(hào)： | HCC4031BF |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64-STAGE STATIC SHIFT REGISTER |
| 中文描述： | 64階段靜態(tài)移位寄存器 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 241K |
| 代理商： | HCC4031BF |
DYNAMIC ELECTRICAL CHARACTERISTICS
(T
amb
= 25
°
C, C
L
= 50pF, R
L
= 200k
,
typical temperature coefficient for all V
DD
values is 0.3%/
°
C, all input rise and fall times = 20ns)
Test Conditions
Value
Typ.
250
110
90
190
80
65
100
50
40
100
50
40
50
25
20
30
15
10
30
15
10
120
50
40
4
10
12
Symbol
Parameter
V
D D
(V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Min.
Max.
500
220
180
380
160
130
200
100
80
200
100
80
100
50
40
60
30
20
60
30
20
240
100
80
Unit
t
PHL
,
t
PLH
, t
PLH
Propagation Delay Time :
Clock to Q,
Clock to Q
ns
t
PHL
,
t
PLH
, t
PHL
Propagation Delay Time :
Clock to Q’
Clock to Q
ns
Clock to CL
D
ns
t
THL’
, t
TLH
Transition Time :
(any output, except Qt
THL
)
ns
t
THL
Q,
ns
t
setup
Data Setup Time
ns
t
hold
Data Hold Time
ns
t
W
Clock Pulse Width
ns
f
max
Maximum Clock Input
Frequency**
2
5
6
MHz
t
r
, t
f
Clock Input Rise or Fall Time*
1000
1000
200
μ
s
*
the propagation delay at 50pF and the transmition time of the output driving stage.
*
* Maximum Clock Frequency for Cascaded Units;
a) Using Delayed Clock Feature in Recirculation Mode :
fmax =
(n-1) CLD prop. delay 1
b) Not Usng Delaye Clock :
fmax =
propagation delay + set-up time
If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of
1
HCC/HCF4031B
5/12
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCC4032B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:TRIPLE SERIAL ADDERS |
| HCC4032BC1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:TRIPLE SERIAL ADDERS |
| HCC4032BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| HCC4032BEY | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:TRIPLE SERIAL ADDERS |
| HCC4032BF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:TRIPLE SERIAL ADDERS |
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