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參數(shù)資料
| 型號： | HCC4030B |
| 廠商： | 意法半導體 |
| 英文描述： | QUAD EXCLUSIVE-OR GATE |
| 中文描述： | 四異或門 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 276K |
| 代理商： | HCC4030B |
The two’scomplement adder-substractor can add or substract any two of the numbers in table 1. For exam-
ple :
a) 2
SIGN
+ =
BIT
–5 X
0
0
0
0
0
0
1
0
2 +
Y
1
1
1
1
1
0
1
1
–5 +
CI
0
S 0 1
1
1
1
1
1
0
1 = –3
CO
Table 1 :
Two’sComplement Numbers and Their Equivalent Decimal Values.
X8
X7
X6
X5
X4
X3
X2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
TEST CIRCUITS
QuiescentDevice Current.
Input Voltage.
Input Leakage Current.
SIGN
BIT
b) –2
– = X
–5
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
0
0 –2 +
1
–5
0
1
1
= 3
Y
Y
CL
S 1 0
CO
+
0
0
0
0
0
1
X1
0
1
0
1
X8
1
1
1
1
1
X7
1
1
1
1
1
X6
1
1
1
1
1
X5
1
1
1
1
1
X4
1
1
1
1
1
X3
1
1
1
1
0
X2
1
1
0
0
1
X1
1
0
1
0
1
=
=
=
=
0
1
2
3
=
=
=
=
=
-1
-2
-3
-4
-5
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
=
=
126
127
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
=
=
-127
-128
HCC/HCF4030B
7/12
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