參數(shù)資料
型號(hào): HC595
廠商: System Logic Semiconductor Co., Ltd.
英文描述: 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
中文描述: 8位Serial-Input/Serial或并行輸出移位與鎖存3注冊(cè)態(tài)輸出
文件頁(yè)數(shù): 6/10頁(yè)
文件大小: 81K
代理商: HC595
SL74HC595
S ystem Logic
Semiconductor
SLS
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
85
°
C
125
°
C
Unit
T
su
Minimum Setup Time,Serial Data
Input A to Shift Clock (Figure 5)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
T
su
Minimum Setup Time, Shift Clock to
Latch Clock (Figure 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
t
h
Minimum Hold Time, Shift Clock to
Serial Data Input A (Figure 5)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
T
rec
Minimum Recovery Time, Reset
Inactive to Shift Clock (Figure 2)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
T
w
Minimum Pulse Width, Reset (Figure
2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
T
w
Minimum Pulse Width, Shift Clock
(Figure 1)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
T
w
Minimum Pulse Width, Latch Clock
(Figure 6)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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