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參數(shù)資料
| 型號： | HC5526IP |
| 廠商： | INTERSIL CORP |
| 元件分類： | 模擬傳輸電路 |
| 英文描述： | ITU CO/PABX SLIC with Low Power Standby |
| 中文描述： | TELECOM-SLIC, PDIP22 |
| 封裝： | PLASTIC, DIP-22 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 176K |
| 代理商： | HC5526IP |
70
SLIC Operating States
Power-Up Sequence
The HC5526 has
no
required power-up sequence. This is a
result of the
D
ielectrically
I
solated (DI) process used in the
fabrication of the part. By using the DI process, care is no
longer required to insure that the substrate be kept at the
most negative potential as with junction isolated ICs.
Printed Circuit Board Layout
Care in the printed circuit board layout is essential for proper
operation. All connections to the RSN pin should be made as
close to the device pin as possible, to limit the interference
that might be injected into the RSN terminal. It is good
practice to surround the RSN pin with a ground plane.
The analog and digital grounds should be tied together at
the device.
Notes
2. OverloadLevel(Two-Wireport).
The overload level is specified
at the 2-wire port (V
TR0
) with the signal source at the 4-wire
receive port (E
RX
). I
DCMET
= 30mA, increase the amplitude of
E
RX
until 1% THD is measured at V
TRO
. Reference Figure 1.
3. LongitudinalImpedance.
The longitudinal impedance is com-
puted using the following equations, where TIP and RING volt-
ages are referenced to ground. L
ZT
, L
ZR
, V
T
, V
R
, A
R
and A
T
are defined in Figure 2.
(TIP) L
ZT
= V
T
/A
T
,
(RING) L
ZR
= V
R
/A
R
,
where: E
L
= 1V
RMS
(0Hz to 100Hz).
4. Longitudinal Current Limit (Off-Hook Active).
Off-Hook
tive, C
1
= 1, C
2
= 0) longitudinal current limit is determined by
increasing the amplitude of E
L
(Figure 3A) until the 2-wire
longitudinal balance drops below 45dB. DET pin remains low
(no false detection).
(Ac-
5. Longitudinal Current Limit (On-Hook Standby).
On-Hook
(Active, C
1
= 1, C
2
= 1) longitudinal current limit is determined
by increasing the amplitude of E
L
(Figure 3B) until the 2-wire
longitudinal balance drops below 45dB. DET pin remains high
(no false detection).
6. LongitudinaltoMetallicBalance.
The longitudinal to metallic
balance is computed using the following equation:
BLME = 20
log (E
L
/V
TR
), where: E
L
and V
TR
are defined in
Figure 4.
7. Metallic to Longitudinal FCC Part 68, Para 68.310.
The
metallic to longitudinal balance is defined in this spec.
8. LongitudinaltoFour-WireBalance.
The longitudinal to 4-wire
balance is computed using the following equation:
BLFE = 20
log (E
L
/V
TX
),: E
L
and V
TX
are defined in Figure 4.
9. MetallictoLongitudinalBalance.
The metallic to longitudinal
balance is computed using the following equation:
BMLE = 20
log (E
TR
/V
L
), E
RX
= 0,
where: E
TR
, V
L
and E
RX
are defined in Figure 5.
10. Four-WiretoLongitudinalBalance.
The 4-wire to longitudinal
balance is computed using the following equation:
BFLE = 20
log (E
RX
/V
L
), E
TR
= source is removed,
where: E
RX
, V
L
and E
TR
are defined in Figure 5.
TABLE 1. LOGIC TRUTH TABLE
E0
E1
C1
C2
SLIC OPERATING STATE
ACTIVE DETECTOR
DET OUTPUT
0
0
0
0
Open Circuit
No Active Detector
Logic Level High
0
0
0
1
Active
Ground Key Detector
Ground Key Status
0
0
1
0
Ringing
No Active Detector
Logic Level High
0
0
1
1
Standby
Ground Key Detector
Ground Key Status
0
1
0
0
Open Circuit
No Active Detector
Logic Level High
0
1
0
1
Active
Loop Current Detector
Loop Current Status
0
1
1
0
Ringing
Ring Trip Detector
Ring Trip Status
0
1
1
1
Standby
Loop Current Detector
Loop Current Status
1
0
0
0
Open Circuit
No Active Detector
Logic Level High
1
0
0
1
Active
Ground Key Detector
1
0
1
0
Ringing
No Active Detector
1
0
1
1
Standby
Ground Key Detector
1
1
0
0
Open Circuit
No Active Detector
1
1
0
1
Active
Loop Current Detector
1
1
1
0
Ringing
Ring Trip Detector
1
1
1
1
Standby
Loop Current Detector
HC5526
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