參數(shù)資料
型號: HC5517B
廠商: Intersil Corporation
英文描述: Low Cost 3 REN Ringing SLIC for ISDN Modem/TA and WL
中文描述: 低成本三任振鈴用戶接口的ISDN調(diào)制解調(diào)器/電訊和WL
文件頁數(shù): 6/11頁
文件大?。?/td> 88K
代理商: HC5517B
66
Circuit Operation and Design Information
Through SLIC Ringing
The HC5517B uses linear amplification to produce the ringing
signal. As a result the ringing SLIC can produce sinusoid,
trapezoid or square wave ringing signals. Regardless of the
wave shape, the ringing signal is balanced. The balanced
waveform is another way of saying that the tip and ring DC
potentials are the same during ringing.
Trapezoidal Ringing
The trapezoidal ringing waveform provides a larger RMS
voltage to the handset. Larger RMS voltages to the handset
provide more power for ringing and also increase the loop
length supported by the ringing SLIC.
One set of component values will satisfy the entire ringing
loop range of the SLIC. A single resistor sets the open circuit
RMS ringing voltage, which will set the crest factor of the ring-
ing waveform. The crest factor of the HC5517B ringing wave-
form is independent of the ringing load (REN) and the loop
length. Another robust feature of the HC5517B ringing SLIC is
the ring trip detector circuit. The suggested values for the ring
trip detector circuit cover quite a large range of applications.
The assumptions used to design the trapezoidal ringing
application circuit are listed below:
Loop current limit set to 25mA.
Impedance matching is set to 600
resistive.
2-wire surge protection is not required.
System able to monitor RTD and SHD.
Logic ringing signal is used to drive RC trapezoid network.
Crest Factor Programming
As previously mentioned, a single resistor is required to set
the crest factor of the trapezoidal waveform. The only design
variable in determining the crest factor is the battery voltage.
The battery voltage limits the peak signal swing and there-
fore directly determines the crest factor.
A set of tables will be provided to allow selection of the crest
factor setting resistor. The tables will include crest factors
below the Bellcore minimum of 1.2 since many ringing SLIC
applications are not constrained by Bellcore requirements.
The RMS voltage listed in the table is the open circuit RMS
voltage generated by the SLIC.
SLIC DESIGN EQUATIONS
FUNCTION
EQUATION
DEFINITION OF TERMS
2-Wire to 4-Wire Gain
V
OUT1
= SLIC 4-wire Output
V
2w
= Voltage across 2-wire load
Z
2W
= 2-Wire Impedance
4-Wire To 2-wire Gain
V
2W
= Voltage Across 2-Wire Load
V
RX
= SLIC 4-Wire Input
Z
2W
= 2-Wire Impedance
Z
SLIC
= SLIC Synthesized Impedance
4-Wire To 4-wire Gain
V
OUT1
= SLIC 4-Wire Output
V
RX
= SLIC 4-Wire Input
Z
2W
= 2-Wire Impedance
Z
SLIC
= SLIC Synthesized Impedance
Loop Current Limit Programming
I
LIMIT
= Programmed Loop Current Limit
R
IL1
= Programming Resistor
R
IL2
= Programming Resistor
Impedance Matching
Z
2W
= 2-Wire Impedance
K = 100
V
2W
------------------
2w
----------
R
RF
-----------
=
V
RX
-----------
2
Z
2W
Z
SLIC
------------+
=
V
RX
------------------
2
Z
2W
Z
SLIC
--------------+
2W
-----------
R
RF
-----------
=
I
LIMIT
0.6
-------------------------------------------------
(
)
R
IL2
R
+
(
)
=
R
ZO
K
Z
2W
100
(
)
=
R
RF
K 200 2
=
TABLE 1. CREST FACTOR PROGRAMMING RESISTOR FOR
V
BAT
= -80V
RTRAP
CF
RMS
RTRAP
CF
RMS
0
1.10
65.0
825
1.25
57.6
389
1.15
62.6
964
1.30
55.4
640
1.20
60.0
1095
1.35
53.3
TABLE 2. CREST FACTOR PROGRAMMING RESISTOR FOR
V
BAT
= -75V
RTRAP
CF
RMS
RTRAP
CF
RMS
0
1.10
60.9
1010
1.25
53.7
500
1.15
58.3
1190
1.30
51.6
791
1.20
55.9
1334
1.35
49.7
HC5517B
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