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參數(shù)資料
| 型號： | HC55121IMZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 24/36頁 |
| 文件大小： | 0K |
| 描述： | IC SLIC UNIVERSAL LP 28-PLCC |
| 標準包裝： | 37 |
| 系列： | UniSLIC14 |
| 功能： | 用戶線路接口概念（SLIC） |
| 電路數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 2.25mA |
| 功率（瓦特）： | 1.5W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 包括： | 電池跟蹤抗削頂失真，回路和接地鍵檢測，振鈴控制 |
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30
FN4659.13
June 1, 2006
88
8
VBH
High Battery Supply (negative with respect to GND).
99
9
VBL
Low Battery Supply (negative with respect to GND, magnitude
≤ VBH).
10
RDC_RAC
Resistive Feed/Anti Clipping - Performs anti clipping function on constant current application and sets
the slope of the resistive feed curve for constant voltage applications.
11
14
CRT_REV
_LVM
Ring Trip, Soft Polarity Reversal and Line Voltage Measurement - A capacitor when placed between the
CRT_REV_LVM pin and +5V performs 3 mutually exclusive functions. When the SLIC is configured in the
Ringing mode it provides filtering of the ringing signal to prevent false detect. When the SLIC is transitioning
between the Forward Active State and Reverse Active State it provides Soft Polarity Reversal and performs
charge storage in the Line Voltage Measurement State. Recommended value 0.47
F.
12
11
CDC
Filter Capacitor - The CDC Capacitor removes the VF signals from the battery feed control loop.
13
12
DT
Tip side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external network
to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DT is more
negative than the voltage on DR.
14
13
DR
Ring Side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external
network to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DR is
more positive than the voltage on DT.
-
15
-
C5
Activates Test Relay TRLY2. TTL Compatible Logic Input. C5 input high, test relay TRLT2 Low(ON).
C5 input floating, test relay TRLY2 High(OFF). This is due to an internal 100k
pull down resistor.
-
16
-
C4
Activates Test Relay TRLY1. TTL Compatible Logic Input. C4 input high, test relay TRLT1 Low(ON).
C4 input floating, test relay TRLY1 High(OFF). This is due to an internal 100k
pull down resistor.
15
17
16
C3
TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the
SLIC. Reference Table 1 for details.
16
18
17
C2
TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the
SLIC. Reference Table 1 for details.
17
19
18
C1
TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the
SLIC. Reference Table 1 for details.
18
20
19
SHD
Switch Hook Detect - Active during off hook, ground key and loopback. Reference Table 1 for details.
21
15
GKD_LVM
Ground Key Detector and Line Voltage Measurement - Reference Table 1 for details.
20
22
20
VCC
5V Supply.
21
23
21
RD
Loop Current Threshold Programming Pin - A resistor between this pin and ground will determine the
trigger level for the loop current detect circuit. See Equation 7.
22
24
22
ROH
Off Hook Overload Setting Resistor - Used to set combined overhead for voice and pulse metering
signals. See Equation 10.
23
25
23
ILIM
Current Limit Programming Pin - A resistor between this pin and ground will determine the constant
current limit of the feed curve. See Equation 11.
24
26
24
RSYNC_REV
Ring Synchronization Input and Reversal Time Setting. A resistor between this pin and GND
determines the polarity reversal time. Synchronization of the closing of the relay at zero voltage is
achieved via a ring sync pulse (5V to 0V) synchronized to the ring signal zero voltage crossing
(Reference Figure 18).
25
27
28
AGND
Analog ground
26
28
25
VRX
Receive Input - Ground referenced 4-wire side.
27
29
26
SPM
Pulse Metering Signal Input. If pulse metering is not used, then this pin should be grounded as close
to the device pin as possible. Input impedance to ground = 125k
.
28
30
27
VTX
Transmit Output - Ground referenced 4-wire side.
-
31
-
TRLY2
Test Relay Driver 2. Open Collector Transistor. Internal Clamp between it’s output and ground
elimnates the need to place an external snubber diode across Test Relay Driver. TRLY2 may be
connected to maximum of 14V.
-
32
-
TRLY1
Test Relay Driver 1. Open Collector Transistor. Internal Clamp between it’s output and ground
elimnates the need to place an external snubber diode across Test Relay Driver. TRLY1 may be
connected to maximum of 14V.
Pin Descriptions (Continued)
28
PIN
PLCC
32
PIN
PLCC
28
PIN
SOIC
SYMBOL
DESCRIPTION
HC55120, HC55121, HC55130, HC55140, HC55142, HC55143, HC55150
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