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參數(shù)資料
| 型號： | HC534 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | Voltage Regulator IC; Package/Case:3-TO-3; Current Rating:1.5A; Output Voltage Max:-12V; Voltage Regulator Type:Fixed Voltage; Mounting Type:Through Hole |
| 中文描述： | 八路三態(tài)反相D觸發(fā)器 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大小： | 53K |
| 代理商： | HC534 |
SL74HC534
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
5.0
24
28
4.0
20
24
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q (Figures
1 and 4)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PZH
, t
PZL
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
C
OUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
-
15
15
15
pF
Power Dissipation Capacitance (Per Flip-Flop)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
34
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
t
SU
Minimum Setup Time, Data to
Clock (Figure 3)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
t
h
Minimum Hold Time, Clock to
Data (Figure 3)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
r,
t
f
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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