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參數(shù)資料
| 型號(hào)： | HC373M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Bipolar Transistor; Collector Emitter Voltage, Vceo:60V; DC Current Gain Min (hfe):100; Collector Current:10A; Package/Case:3-TO-127; Transistor Polarity:NPN |
| 中文描述： | 八路透明D類鎖存器具有三態(tài)輸出 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 310K |
| 代理商： | HC373M |
CD54HC373, CD74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS452A
–
FEBRUARY 2001
–
REVISED APRIL 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Test
Point
From Output
Under Test
CL
(see Note A)
VCC
S1
S2
LOAD CIRCUIT
PARAMETER
tPZH
tpd or tt
tdis
ten
tPZL
tPHZ
tPLZ
Open
Closed
S1
Closed
Open
S2
Open
Closed
Closed
Open
Open
Open
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
I. All parameters and waveforms are not applicable to all devices.
RL = 1 k
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
th
tsu
50% VCC
10%
tf
50%
10%
90%
90%
VCC
VCC
0 V
0 V
tr
Reference
Input
Data
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% VCC
510%
tf
50%
10%
90%
90%
VCC
VOH
VOL
0 V
tr
Input
In-Phase
Output
50% VCC
tPLH
tPHL
510%
50%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
50% VCC
50% VCC
VCC
Output
Control
Output
Waveform 1
(see Note B)
Output
Waveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈
VCC
0 V
50% VCC
10%
50% VCC
≈
0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
50% VCC
50% VCC
90%
VCC
VOLTAGE WAVEFORMS
RECOVERY TIME
50% VCC
VCC
0 V
CLR
Input
CLK
50% VCC
VCC
trec
0 V
Figure 1. Load Circuit and Voltage Waveforms
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