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參數(shù)資料
| 型號： | HC161 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable Counters |
| 中文描述： | 可預置計數(shù)器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 85K |
| 代理商： | HC161 |
SL74HC161
S ystem Logic
Semiconductor
SLS
V
CC
=Pin 16
GND=Pin 8
The flip-flops shown in the circuit diagrams are Toggle-Enable flip-flops. A Toggle-Enable flip-flop is a
combination of a D flip-flop and a T flip-flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load
signal is used to disable the Toggle input (Tn) of the flip-flop. The logic level at the Pn input is then clocked to
the Q output of the flip-flop on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip-
flop low.
Figure 7.Expanded logic diagram
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