參數資料
型號: HC109
廠商: System Logic Semiconductor Co., Ltd.
英文描述: Dual J-K Flip-Flop with Set and Reset
中文描述: 雙JK觸發(fā)器的設置和復位
文件頁數: 4/5頁
文件大小: 47K
代理商: HC109
SL74HC109
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
85
°
C
125
°
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6
30
35
4.8
24
28
4.0
20
24
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
t
PLH
, t
PHL
Maximum Propagation Delay , Set or Reset to Q or
Q (Figures 2 and 4)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Flip-Flop)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC
f+I
CC
V
CC
40
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to -55
°
C
85
°
C
125
°
C
Unit
t
SU
Minimum Setup Time, J or K to
Clock (Figure 3)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
h
Minimum Hold Time, Clock to
J or K (Figure 3)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
rec
Minimum Recovery Time, Set
or Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
t
w
Minimum Pulse Width, Set or
Reset (Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
12
24
20
ns
t
w
Minimum Pulse Width,Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
12
24
20
ns
t
r,
t
f
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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參數描述
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HC1-100-R 功能描述:固定電感器 10uH 5.3A 5.7mOhms RoHS:否 制造商:AVX 電感:10 uH 容差:20 % 最大直流電流:1 A 最大直流電阻:0.075 Ohms 工作溫度范圍:- 40 C to + 85 C 自諧振頻率:38 MHz Q 最小值:40 尺寸:4.45 mm W x 6.6 mm L x 2.92 mm H 屏蔽:Shielded 端接類型:SMD/SMT 封裝 / 箱體:6.6 mm x 4.45 mm
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