參數(shù)資料
型號(hào)： HB28A896IA1
元件分類(lèi)： PROM
英文描述： 448M X 16 FLASH 5V PROM CARD, XMA68
封裝： CARD-68
文件頁(yè)數(shù)： 34/47頁(yè)
文件大?。?/td> 146K
代理商： HB28A896IA1
HB28A896IA1, HB28A512IA1
4
Card Pin Explanation
Host Interface Pin Explanation
Signal name
Direction Pin No.
Description
-RESET
I
58
This signal is active low host reset pin. Once the host asserts
-RESET, the host must keep -RESET asserting for at least 25
s.
A2 to A0
I
27, 28, 29
Address bus of Host I/F is A2 to A0. A2 is MSB and A0 is LSB.
D15 to D0
I/O
41, 40, 39
38, 37, 66
65, 64, 6
5, 4, 3
2, 32, 31
30
Data bus of Host I/F is D15 to D0. D0 is the LSB of the even
byte of the word. D8 is the LSB of the odd byte of the word.
-CS0
-CS1
I
7, 42
-CS1 is used for selecting the Alternate Status Register and
the Device Control Register. -CS0 is used for the other task
file registers.
-IOWR
I
45
-IOWR is used for control of write data in I/O task file area.
STOP
(Ultra DMA mode)
This signal must be negated prior to initiation of an Ultra DMA
burst. And this signal must be negated before data is
transferred in an Ultra DMA burst. Assertion during an Ultra
DMA burst flowing indicates the termination of the Ultra DMA
burst.
-IORD
I
44
-IORD is used for control of read data in I/O task file area.
-HDMARDY
(Ultra DMA data-in)
-HDMARDY is a data flow control signal. The host shall assert
this signal to indicate that the host is ready to receive Ultra
DMA data-in bursts. The host may negate this signal to
indicate that the host pauses an Ultra DMA data-in burst.
HSTROBE
(Ultra DMA data-out)
HSTROBE is a data strobe signal. Both the rising and falling
edges of HSTROBE latch the data of D15 to D0 into this card.
Stopping generating HSTROBE edges indicates that the host
pauses an Ultra DMA data-out burst.
-DMACK
I
61
This signal is used for response to asserting DMARQ to initiate
DMA transfers.
-IOCS16
O
33
This output signal is asserted low when this device is expecting
a word data transfer cycle. Initial mode is 16-bit. If the user
issues a Set Feature Command to put the device in Byte
access mode, the card permits 8-bit accesses.
INTRQ
O
16
This signal is the active high Interrupt Request to the host.
DMARQ
O
60
This signal is asserted high when the card is ready to DMA
data transfers.
-PDIAG
I/O
63
-PDIAG is the Pass Diagnostic signal in Master/Slave
handshake protocol.
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