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參數(shù)資料
| 型號(hào)： | HA13159 |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | FPGA |
| 英文描述： | 200000 SYSTEM GATE 1.8V FPGA - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 37糯】4通道橋接功率IC |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 85K |
| 代理商： | HA13159 |
HA13159
Rev.2, Jul. 1999, page 7 of 15
Point of Application Board Design
1. Notes on Application Board’s Pattern Design
For increasing stability, the connected line of V
CC
and OUTGND is better to be made wider and lower
impedance.
For increasing stability, it is better to place the capacitor between V
CC
and GND (0.1
μ
F) close to IC.
It is better to place the grounding of resistor (Rg), between input line and ground, close to INGND (Pin
12) because if OUTGND is connected to the line between Rg and INGND, THD will become worse due
to current from OUTGND.
Rg
0.1
μ
F
V
CC
1
12
6
5
4
3
Figure 1 Notes on Application Board’s Pattern Design
2. How to Reduce the Popping Noise by Muting Circuit
At normal operating circuit, Muting circuit operates at high speed under 1
μ
s.
In case popping noise becomes a problem, it is possible to reduce the popping noise by connecting
capacitor, which determines the switching time constant, between pin 10 and GND. (Following figure
2)
We recommend value of capacitor greater then 1
F.
Also transitional popping noise can be reduced sharply by muting before V
CC
and Standby are ON/OFF.
0 V
5 V
7.5 k
4.7
μ
F
10
Muting
control
Figure 2 How to use Muting Circuit
Table 1
Muting ON/OFF Time
C (
μ
F)
ON Time
OFF Time
nothing
under 1
μ
s
2 ms
under 1
μ
s
2 ms
0.47
4.7
19 ms
19 ms
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