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參數(shù)資料
| 型號(hào)： | HA1-2420-2 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP SAMPLE&HOLD 3.2US 14-DIP |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 放大器類型： | 采樣和保持 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 5 V/µs |
| 增益帶寬積： | 2.5MHz |
| 電流 - 輸入偏壓： | 40nA |
| 電壓 - 輸入偏移： | 2000µV |
| 電流 - 電源： | 3.5mA |
| 電流 - 輸出 / 通道： | 15mA |
| 電壓 - 電源，單路/雙路(±)： | ±12 V ~ 15 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-CERDIP |
| 包裝： | 管件 |
6
FN2856.7
October 24, 2013
Application Information
Offset Adjustment
The offset voltage of the HA-2420, may be adjusted using a
100k
Ω trim pot, as shown in Figure 8. The recommended
adjustment procedure is:
Apply 0V to the sample-and-hold input, and a square wave
to the S/H control.
Adjust the trim pot for 0V output in the hold mode.
Gain Adjustment
The linear variation in pedestal voltage with
sample-and-hold input voltage causes a -0.06% gain error
(CH = 1000pF). In some applications (D/A deglitcher, A/D
converter) the gain error can be adjusted elsewhere in the
system, while in other applications it must be adjusted at the
sample-and-hold. The two circuits shown below demonstrate
how to adjust gain error at the sample-and-hold.
The recommended procedure for adjusting gain error is:
1. Perform offset adjustment.
2. Apply the nominal input voltage that should produce a
+10V output.
3. Adjust the trim pot for +10V output in the hold mode.
4. Apply the nominal input voltage that should produce a
-10V output.
5. Measure the output hold voltage (V-10NOMINAL). Adjust
the trim pot for an output hold voltage of
Figure 8 shows a typical unity gain circuit, with Offset
Zeroing. All of the other normal op amp feedback
configurations may be used with the HA-2420. The input
amplifier may be used as a gated amplifier by utilizing Pin 11
as the output. This amplifier has excellent drive capabilities
along with exceptionally low switch leakage.
The method used to reduce leakage paths on the PC board
and the device package is shown in Figure 9. This guard ring
is recommended to minimize the drift during hold mode.
The hold capacitor should have extremely high insulation
resistance and low dielectric absorption. Polystyrene (below
85°C), Teflon, or Parlene types are recommended.
For more applications, consult Intersil Application Note
, or the factory applications group.
0
+10
5
-5
-10
-15
-20
-25
-30
-35
-10
-5
+5
+10
DC INPUT VOLTAGE (V)
HOLD STEP VOLTAGE (mV)
CH = 100pF
H = 1000pF
CH = 10,000pF
CH = 0.1μF
FIGURE 5. HOLD STEP vs INPUT VOLTAGE
V 10
–
NOMINAL
()
-10V
()
+
2
-----------------------------------------------------------------
-IN
+IN
OUT
S/H
CONTROL
OUTPUT
RI
RF
0.002RF
INPUT
S/H CONTROL INPUT
NOTE: GAIN
R
F
–
R
I
-----------
FIGURE 6. INVERTING CONFIGURATION
+IN
-IN
OUT
S/H
CONTROL
OUTPUT
INPUT
S/H CONTROL
INPUT
NOTE: GAIN ~ 1
R
F
R
I
--------
+
RF
RI
0.002RI
FIGURE 7. NON-INVERTING CONFIGURATION
IN
V-
100k
Ω
OFFSET TRIM (
±25mV RANGE)
OUT
V+
CONTROL
CH
-
+
-
+
FIGURE 8. BASIC SAMPLE-AND-HOLD (TOP VIEW)
HA-2420
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HA1-2420-2B1121-034 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| HA1-2420B1686 DIE | 制造商:Harris Corporation 功能描述: |
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| HA1-2420B2170-002 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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