
Rev. 3.00, 05/03, page xi of xxx
6.2.2
6.2.3
6.2.4
Operating Frequency in Active Mode...............................................................................85
Direct Transition...............................................................................................................85
6.4.1
Direct Transition from Active Mode to Subactive Mode.....................................85
6.4.2
Direct Transition from Subactive Mode to Active Mode.....................................86
Module Standby Function.................................................................................................86
Standby Mode......................................................................................................84
Subsleep Mode.....................................................................................................84
Subactive Mode ...................................................................................................85
6.3
6.4
6.5
Section 7 ROM ................................................................................................. 87
7.1
Block Configuration..........................................................................................................87
7.2
Register Descriptions........................................................................................................89
7.2.1
Flash Memory Control Register 1 (FLMCR1).....................................................89
7.2.2
Flash Memory Control Register 2 (FLMCR2).....................................................90
7.2.3
Erase Block Register 1 (EBR1) ...........................................................................91
7.2.4
Flash Memory Power Control Register (FLPWCR)............................................92
7.2.5
Flash Memory Enable Register (FENR)..............................................................92
7.3
On-Board Programming Modes........................................................................................93
7.3.1
Boot Mode ...........................................................................................................93
7.3.2
Programming/Erasing in User Program Mode.....................................................96
7.4
Flash Memory Programming/Erasing...............................................................................97
7.4.1
Program/Program-Verify.....................................................................................97
7.4.2
Erase/Erase-Verify...............................................................................................99
7.4.3
Interrupt Handling when Programming/Erasing Flash Memory..........................100
7.5
Program/Erase Protection..................................................................................................102
7.5.1
Hardware Protection ............................................................................................102
7.5.2
Software Protection..............................................................................................102
7.5.3
Error Protection....................................................................................................102
7.6
Programmer Mode ............................................................................................................103
7.7
Power-Down States for Flash Memory.............................................................................103
Section 8 RAM ................................................................................................. 105
Section 9 I/O Ports............................................................................................ 107
9.1
Port 1.................................................................................................................................107
9.1.1
Port Mode Register 1 (PMR1).............................................................................108
9.1.2
Port Control Register 1 (PCR1)...........................................................................109
9.1.3
Port Data Register 1 (PDR1)................................................................................109
9.1.4
Port Pull-Up Control Register 1 (PUCR1)...........................................................110
9.1.5
Pin Functions .......................................................................................................110
9.2
Port 2.................................................................................................................................113
9.2.1
Port Control Register 2 (PCR2)...........................................................................113
9.2.2
Port Data Register 2 (PDR2)................................................................................114